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UVM Users Guide 1.2.pdf
1. Overview
1.1 The Typical UVM Testbench Architecture
1.1.1 UVM Testbench
1.1.2 UVM Test
1.1.3 UVM Environment
1.1.4 UVM Scoreboard
1.1.5 UVM Agent
1.1.6 UVM Sequencer
1.1.7 UVM Sequence
1.1.8 UVM Driver
1.1.9 UVM Monitor
1.2 The UVM Class Library
2. Transaction-Level Modeling (TLM)
2.1 Overview
2.2 TLM, TLM-1, and TLM-2.0
2.3 TLM-1 Implementation
2.3.1 Basics
2.3.2 Encapsulation and Hierarchy
2.3.3 Analysis Communication
2.4 TLM-2.0 Implementation
2.4.1 Generic Payload
2.4.2 Core Interfaces and Ports
2.4.3 Blocking Transport
2.4.4 Nonblocking Transport
2.4.5 Sockets
2.4.6 Time
2.4.7 Use Models
3. Developing Reusable Verification Components
3.1 Modeling Data Items for Generation
3.1.1 Inheritance and Constraint Layering
3.1.2 Defining Control Fields (“Knobs”)
3.2 Transaction-Level Components
3.3 Creating the Driver
3.4 Creating the Sequencer
3.5 Connecting the Driver and Sequencer
3.5.1 Basic Sequencer and Driver Interaction
3.5.2 Querying for the Randomized Item
3.5.3 Fetching Consecutive Randomized Items
3.5.4 Sending Processed Data back to the Sequencer
3.5.5 Using TLM-Based Drivers
3.6 Creating the Monitor
3.7 Instantiating Components
3.8 Creating the Agent
3.8.1 Operating Modes
3.8.2 Connecting Components
3.9 Creating the Environment
3.9.1 The Environment Class
3.9.2 Invoking build_phase
3.10 Enabling Scenario Creation
3.10.1 Declaring User-Defined Sequences
3.10.2 Sending Subsequences and Sequence Items
3.10.3 Starting a Sequence on a Sequencer
3.10.4 Overriding Sequence Items and Sequences
3.11 Managing End of Test
3.12 Implementing Checks and Coverage
3.12.1 Implementing Checks and Coverage in Classes
3.12.2 Implementing Checks and Coverage in Interfaces
3.12.3 Controlling Checks and Coverage
4. Using Verification Components
4.1 Creating a Top-Level Environment
4.2 Instantiating Verification Components
4.3 Creating Test Classes
4.4 Verification Component Configuration
4.4.1 Verification Component Configurable Parameters
4.4.2 Verification Component Configuration Mechanism
4.4.3 Choosing between uvm_resource_db and uvm_config_db
4.4.4 Using a Configuration Class
4.5 Creating and Selecting a User-Defined Test
4.5.1 Creating the Base Test
4.5.2 Creating Tests from a Test-Family Base Class
4.5.3 Test Selection
4.6 Creating Meaningful Tests
4.6.1 Constraining Data Items
4.6.2 Data Item Definitions
4.6.3 Creating a Test-Specific Frame
4.7 Virtual Sequences
4.7.1 Creating a Virtual Sequencer
4.7.2 Creating a Virtual Sequence
4.7.3 Controlling Other Sequencers
4.7.4 Connecting a Virtual Sequencer to Subsequencers
4.8 Checking for DUT Correctness
4.9 Scoreboards
4.9.1 Creating the Scoreboard
4.9.2 Adding Exports to uvm_scoreboard
4.9.3 Requirements of the TLM Implementation
4.9.4 Defining the Action Taken
4.9.5 Adding the Scoreboard to the Environment
4.9.6 Summary
4.10 Implementing a Coverage Model
4.10.1 Selecting a Coverage Method
4.10.2 Implementing a Functional Coverage Model
4.10.3 Enabling and Disabling Coverage
5. Using the Register Layer Classes
5.1 Overview
5.2 Usage Model
5.2.1 Sub-register Access
5.2.2 Mirroring
5.2.3 Memories are not Mirrored
5.3 Access API
5.3.1 read / write
5.3.2 peek / poke
5.3.3 get / set
5.3.4 randomize
5.3.5 update
5.3.6 mirror
5.3.7 Concurrent Accesses
5.4 Coverage Models
5.4.1 Predefined Coverage Identifiers
5.4.2 Controlling Coverage Model Construction and Sampling
5.5 Constructing a Register Model
5.5.1 Field Types
5.5.2 Register Types
5.5.3 Register File Types
5.5.4 Memory Types
5.5.5 Block Types
5.5.6 Packaging a Register Model
5.5.7 Maximum Data Size
5.6 Back-door Access
5.6.1 Back-door read/write vs. peek/poke
5.6.2 Hierarchical HDL Paths
5.6.3 VPI-based Back-door Access
5.6.4 User-defined Back-door Access
5.6.5 Back-door Access for Protected Memories
5.6.6 Active Monitoring
5.7 Special Registers
5.7.1 Pre-defined Special Registers
5.7.2 Unmapped Registers and Memories
5.7.3 Aliased Registers
5.7.4 Unimplemented Registers
5.7.5 RO and WO Registers Sharing the Same Address
5.8 Integrating a Register Model in a Verification Environment
5.9 Integrating a Register Model
5.9.1 Transaction Adapter
5.9.2 Integrating Bus Sequencers
5.9.3 Integrating the Register Model with a Bus Monitor
5.10 Randomizing Field Values
5.11 Pre-defined Sequences
6. Advanced Topics
6.1 The uvm_component Base Class
6.2 The Built-In Factory and Overrides
6.2.1 About the Factory
6.2.2 Factory Registration
6.2.3 Component Overrides
6.3 Callbacks
6.3.1 Use Model
6.3.2 Example
6.4 The Sequence Library
6.5 Advanced Sequence Control
6.5.1 Implementing Complex Scenarios
6.5.2 Protocol Layering
6.5.3 Generating the Item or Sequence in Advance
6.5.4 Executing Sequences and Items on other Sequencers
6.6 Command Line Interface (CLI)
6.6.1 Introduction
6.6.2 Getting Started
6.6.3 UVM-aware Command Line Processing
6.7 Macros in UVM
7. UBus Verification Component Example
7.1 UBus Example
7.2 UBus Example Architecture
7.3 UBus Top Module
7.4 The Test
7.5 Testbench Environment
7.6 UBus Environment
7.7 UBus Master Agent
7.8 UBus Master Sequencer
7.9 UBus Driver
7.10 UBus Agent Monitor
7.11 UBus Bus Monitor
7.11.1 Collecting Transfers from the Bus
7.11.2 Number of Transfers
7.11.3 Notifiers Emitted by the UBus Bus Monitor
7.11.4 Checks and Coverage
7.12 UBus Interface
8. UBus Specification
8.1 Introduction
8.1.1 Motivation
8.1.2 Bus Overview
8.2 Bus Description
8.2.1 Bus Signals
8.2.2 Clocking
8.2.3 Reset
8.3 Arbitration Phase
8.4 Address Phase
8.4.1 NOP Cycle
8.4.2 Normal Address Phase
8.5 Data Phase
8.5.1 Write Transfer
8.5.2 Error during Write Transfer
8.5.3 Read Transfer
8.5.4 Error during Read Transfer
8.6 How Data is Driven
8.7 Optional Pipelining Scheme
8.7.1 Pipelined Arbitration Phase
8.7.2 Pipelined Address Phase
8.7.3 Pipelined Data Phase
8.8 Example Timing Diagrams
Universal Verification Methodology
(UVM) 1.2 User’s Guide
October 8, 2015
Copyright © 2011 - 2015 Accellera. All rights reserved.
October 8, 2015
UVM 1.2 User’s Guide
Copyright© 2011 - 2015 Accellera Systems Initiative (Accellera). All rights reserved.
Accellera Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USA
Copyright© 2013 - 2015 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices (AMD), 7171 Southwest Parkway, Austin, TX 78735
Copyright© 2011 - 2015 Cadence Design Systems, Inc. (Cadence). All rights reserved.
Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, USA.
Copyright© 2011 - 2015 Mentor Graphics, Corp. (Mentor). All rights reserved.
Mentor Graphics, Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
Copyright© 2013 - 2015 NVIDIA CORPORATION. All rights reserved.
NVIDIA Corporation, 2701 San Tomas Expy, Santa Clara, CA 95050
Copyright© 2011 - 2015 Synopsys, Inc. (Synopsys). All rights reserved.
Synopsys, Inc., 690 E. Middlefield Rd, Mountain View, CA 94043
This product is licensed under the Apache Software Foundation’s Apache License, Version 2.0,
January 2004. The full license is available at: http://www.apache.org/licenses/.
Notices
While this guide offers a set of instructions to perform one or more specific verification tasks, it should be
supplemented by education, experience, and professional judgment. Not all aspects of this guide may be
applicable in all circumstances. The UVM 1.2 User’s Guide does not necessarily represent the standard of
care by which the adequacy of a given professional service must be judged nor should this document be
applied without consideration of a project’s unique aspects. This guide has been approved through the
Accellera consensus process and serves to increase the awareness of information and approaches in
verification methodology. This guide may have several recommendations to accomplish the same thing and
may require some judgment to determine the best course of action.
The UVM 1.2 Class Reference represents the foundation used to create the UVM 1.2 User’s Guide. This
guide is a way to apply the UVM 1.2 Class Reference, but is not the only way. Accellera believes standards
are an important ingredient to foster innovation and continues to encourage industry innovation based on its
standards.
Suggestions for improvements to the UVM 1.2 User’s Guide are welcome. They should be sent to the UVM
email reflector
uvm-wg@lists.accellera.org
ii
Copyright © 2011 - 2015 Accellera. All rights reserved.
UVM 1.2 User’s Guide
Contents
October 8, 2015
1.
Overview.............................................................................................................................................. 1
1.1 The Typical UVM Testbench Architecture................................................................................ 1
UVM Testbench .......................................................................................................... 2
UVM Test ................................................................................................................... 2
UVM Environment ..................................................................................................... 2
UVM Scoreboard ........................................................................................................ 2
UVM Agent ................................................................................................................ 2
UVM Sequencer ......................................................................................................... 3
UVM Sequence ........................................................................................................... 3
UVM Driver ................................................................................................................ 3
UVM Monitor ............................................................................................................. 4
1.2 The UVM Class Library............................................................................................................. 4
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
2.
Transaction-Level Modeling (TLM) ................................................................................................... 7
2.3.1
2.3.2
2.3.3
2.1 Overview .................................................................................................................................... 7
2.2 TLM, TLM-1, and TLM-2.0 ...................................................................................................... 7
2.3 TLM-1 Implementation.............................................................................................................. 8
Basics .......................................................................................................................... 8
Encapsulation and Hierarchy .................................................................................... 12
Analysis Communication .......................................................................................... 14
2.4 TLM-2.0 Implementation......................................................................................................... 16
Generic Payload ........................................................................................................ 16
Core Interfaces and Ports .......................................................................................... 19
Blocking Transport ................................................................................................... 20
Nonblocking Transport ............................................................................................. 20
Sockets ...................................................................................................................... 22
Time .......................................................................................................................... 25
Use Models ............................................................................................................... 27
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
3.
Developing Reusable Verification Components................................................................................ 29
3.1.1
3.1.2
3.1 Modeling Data Items for Generation ....................................................................................... 29
Inheritance and Constraint Layering ......................................................................... 30
Defining Control Fields (“Knobs”) ........................................................................... 31
3.2 Transaction-Level Components ............................................................................................... 32
3.3 Creating the Driver................................................................................................................... 34
3.4 Creating the Sequencer............................................................................................................. 35
3.5
Connecting the Driver and Sequencer..................................................................................... 35
Basic Sequencer and Driver Interaction ................................................................... 36
3.5.1
Querying for the Randomized Item .......................................................................... 36
3.5.2
Fetching Consecutive Randomized Items ................................................................. 37
3.5.3
3.5.4
Sending Processed Data back to the Sequencer ........................................................ 37
Using TLM-Based Drivers ....................................................................................... 38
3.5.5
3.6 Creating the Monitor ................................................................................................................ 38
3.7
Instantiating Components......................................................................................................... 40
3.8 Creating the Agent ................................................................................................................... 41
Operating Modes ....................................................................................................... 41
Connecting Components ........................................................................................... 43
3.8.1
3.8.2
Copyright © 2011 - 2015 Accellera. All rights reserved.
iii
October 8, 2015
UVM 1.2 User’s Guide
3.9.1
3.9.2
3.9 Creating the Environment ........................................................................................................ 43
The Environment Class ............................................................................................. 43
Invoking build_phase ................................................................................................ 44
3.10 Enabling Scenario Creation...................................................................................................... 44
3.10.1 Declaring User-Defined Sequences .......................................................................... 45
3.10.2 Sending Subsequences and Sequence Items ............................................................. 45
3.10.3 Starting a Sequence on a Sequencer ......................................................................... 48
3.10.4 Overriding Sequence Items and Sequences .............................................................. 49
3.11 Managing End of Test.............................................................................................................. 50
3.12 Implementing Checks and Coverage........................................................................................ 52
Implementing Checks and Coverage in Classes ....................................................... 52
3.12.1
3.12.2
Implementing Checks and Coverage in Interfaces ................................................... 54
3.12.3 Controlling Checks and Coverage ............................................................................ 54
4.
Using Verification Components ........................................................................................................ 55
4.5.1
4.5.2
4.5.3
4.6.1
4.6.2
4.6.3
4.4.1
4.4.2
4.4.3
4.4.4
4.1 Creating a Top-Level Environment.......................................................................................... 55
4.2
Instantiating Verification Components .................................................................................... 56
4.3 Creating Test Classes ............................................................................................................... 58
4.4 Verification Component Configuration ................................................................................... 58
Verification Component Configurable Parameters ................................................... 58
Verification Component Configuration Mechanism ................................................ 59
Choosing between uvm_resource_db and uvm_config_db ...................................... 60
Using a Configuration Class ..................................................................................... 60
4.5 Creating and Selecting a User-Defined Test............................................................................ 61
Creating the Base Test .............................................................................................. 61
Creating Tests from a Test-Family Base Class ......................................................... 61
Test Selection ............................................................................................................ 62
4.6 Creating Meaningful Tests....................................................................................................... 63
Constraining Data Items ........................................................................................... 63
Data Item Definitions ................................................................................................ 64
Creating a Test-Specific Frame ................................................................................ 64
4.7 Virtual Sequences..................................................................................................................... 65
Creating a Virtual Sequencer .................................................................................... 66
Creating a Virtual Sequence ..................................................................................... 67
Controlling Other Sequencers ................................................................................... 68
Connecting a Virtual Sequencer to Subsequencers .................................................. 69
4.8 Checking for DUT Correctness................................................................................................ 70
4.9
Scoreboards .............................................................................................................................. 70
Creating the Scoreboard ............................................................................................ 71
4.9.1
Adding Exports to uvm_scoreboard ......................................................................... 71
4.9.2
Requirements of the TLM Implementation .............................................................. 72
4.9.3
4.9.4
Defining the Action Taken ....................................................................................... 72
Adding the Scoreboard to the Environment ............................................................. 72
4.9.5
4.9.6
Summary ................................................................................................................... 73
4.10 Implementing a Coverage Model............................................................................................. 73
4.10.1 Selecting a Coverage Method ................................................................................... 73
4.10.2
Implementing a Functional Coverage Model ........................................................... 74
4.10.3 Enabling and Disabling Coverage ............................................................................ 74
4.7.1
4.7.2
4.7.3
4.7.4
5.
Using the Register Layer Classes ...................................................................................................... 75
5.1 Overview .................................................................................................................................. 75
5.2 Usage Model ............................................................................................................................ 75
iv
Copyright © 2011 - 2015 Accellera. All rights reserved.
UVM 1.2 User’s Guide
October 8, 2015
5.4.1
5.4.2
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Sub-register Access ................................................................................................... 78
5.2.1
5.2.2 Mirroring ................................................................................................................... 79
5.2.3 Memories are not Mirrored ....................................................................................... 80
5.3 Access API ............................................................................................................................... 80
read / write ................................................................................................................ 80
peek / poke ................................................................................................................ 81
get / set ...................................................................................................................... 81
randomize .................................................................................................................. 81
update ........................................................................................................................ 82
mirror ........................................................................................................................ 82
Concurrent Accesses ................................................................................................. 82
5.4 Coverage Models...................................................................................................................... 83
Predefined Coverage Identifiers ............................................................................... 83
Controlling Coverage Model Construction and Sampling ....................................... 83
5.5 Constructing a Register Model................................................................................................. 84
5.5.1
Field Types ............................................................................................................... 84
5.5.2
Register Types .......................................................................................................... 90
5.5.3
Register File Types ................................................................................................... 93
5.5.4 Memory Types .......................................................................................................... 95
Block Types .............................................................................................................. 96
5.5.5
5.5.6
Packaging a Register Model ................................................................................... 100
5.5.7 Maximum Data Size ............................................................................................... 100
5.6 Back-door Access................................................................................................................... 101
Back-door read/write vs. peek/poke ....................................................................... 101
5.6.1
Hierarchical HDL Paths .......................................................................................... 102
5.6.2
VPI-based Back-door Access ................................................................................. 103
5.6.3
User-defined Back-door Access ............................................................................. 104
5.6.4
Back-door Access for Protected Memories ............................................................ 104
5.6.5
5.6.6
Active Monitoring ................................................................................................... 105
Special Registers .................................................................................................................... 106
Pre-defined Special Registers ................................................................................. 107
5.7.1
Unmapped Registers and Memories ....................................................................... 108
5.7.2
Aliased Registers .................................................................................................... 110
5.7.3
5.7.4
Unimplemented Registers ....................................................................................... 112
5.7.5
RO and WO Registers Sharing the Same Address ................................................. 113
Integrating a Register Model in a Verification Environment................................................. 114
Integrating a Register Model.................................................................................................. 114
Transaction Adapter ................................................................................................ 115
5.9.1
5.9.2
Integrating Bus Sequencers .................................................................................... 117
Integrating the Register Model with a Bus Monitor ............................................... 123
5.9.3
5.10 Randomizing Field Values..................................................................................................... 125
5.11 Pre-defined Sequences ........................................................................................................... 125
5.7
5.8
5.9
6.
Advanced Topics ............................................................................................................................. 129
6.2.1
6.2.2
6.2.3
6.1 The uvm_component Base Class ........................................................................................... 129
6.2 The Built-In Factory and Overrides ....................................................................................... 129
About the Factory ................................................................................................... 129
Factory Registration ................................................................................................ 130
Component Overrides ............................................................................................. 130
6.3 Callbacks ................................................................................................................................ 133
Use Model ............................................................................................................... 133
Example .................................................................................................................. 134
6.4 The Sequence Library ............................................................................................................ 137
6.3.1
6.3.2
Copyright © 2011 - 2015 Accellera. All rights reserved.
v
October 8, 2015
UVM 1.2 User’s Guide
6.5.1
6.5.2
6.5.3
6.5.4
6.5 Advanced Sequence Control .................................................................................................. 139
Implementing Complex Scenarios .......................................................................... 139
Protocol Layering ................................................................................................... 144
Generating the Item or Sequence in Advance ........................................................ 154
Executing Sequences and Items on other Sequencers ............................................ 156
6.6 Command Line Interface (CLI).............................................................................................. 156
Introduction ............................................................................................................. 156
Getting Started ........................................................................................................ 156
UVM-aware Command Line Processing ................................................................ 157
6.7 Macros in UVM ..................................................................................................................... 158
6.6.1
6.6.2
6.6.3
7.
UBus Verification Component Example ......................................................................................... 161
7.1 UBus Example........................................................................................................................ 161
7.2 UBus Example Architecture................................................................................................... 164
7.3 UBus Top Module.................................................................................................................. 165
7.4 The Test.................................................................................................................................. 166
7.5 Testbench Environment.......................................................................................................... 168
7.6 UBus Environment................................................................................................................. 170
7.7 UBus Master Agent................................................................................................................ 171
7.8 UBus Master Sequencer......................................................................................................... 173
7.9 UBus Driver ........................................................................................................................... 173
7.10 UBus Agent Monitor.............................................................................................................. 174
7.11 UBus Bus Monitor ................................................................................................................. 175
7.11.1 Collecting Transfers from the Bus .......................................................................... 175
7.11.2 Number of Transfers ............................................................................................... 176
7.11.3 Notifiers Emitted by the UBus Bus Monitor .......................................................... 176
7.11.4 Checks and Coverage .............................................................................................. 176
7.12 UBus Interface........................................................................................................................ 176
8.
UBus Specification .......................................................................................................................... 177
8.1
8.2.1
8.2.2
8.2.3
Introduction ............................................................................................................................ 177
8.1.1 Motivation ............................................................................................................... 177
8.1.2
Bus Overview ......................................................................................................... 177
8.2 Bus Description...................................................................................................................... 177
Bus Signals ............................................................................................................. 177
Clocking .................................................................................................................. 178
Reset ........................................................................................................................ 178
8.3 Arbitration Phase.................................................................................................................... 178
8.4 Address Phase ........................................................................................................................ 179
NOP Cycle .............................................................................................................. 179
Normal Address Phase ............................................................................................ 179
8.5 Data Phase.............................................................................................................................. 179
8.5.1 Write Transfer ......................................................................................................... 180
Error during Write Transfer .................................................................................... 180
8.5.2
8.5.3
Read Transfer .......................................................................................................... 180
Error during Read Transfer ..................................................................................... 180
8.5.4
8.6 How Data is Driven................................................................................................................ 181
8.7 Optional Pipelining Scheme................................................................................................... 181
Pipelined Arbitration Phase .................................................................................... 181
Pipelined Address Phase ......................................................................................... 182
Pipelined Data Phase .............................................................................................. 182
8.8 Example Timing Diagrams .................................................................................................... 182
8.4.1
8.4.2
8.7.1
8.7.2
8.7.3
vi
Copyright © 2011 - 2015 Accellera. All rights reserved.
UVM 1.2 User’s Guide
1. Overview
October 8, 2015
This chapter provides a quick overview of UVM by going through the typical testbench architecture and
introducing the terminology used throughout this User’s Guide. Then, it also touches upon the UVM Base
Class Library (BCL) developed by Accellera.
1.1 The Typical UVM Testbench Architecture
The UVM Class Library provides generic utilities, such as component hierarchy, transaction library model
(TLM), configuration database, etc., which enable the user to create virtually any structure he/she wants for
the testbench. This section provides some broad guidelines for a type of recommended testbench
architecture by using one viewpoint of this architecture in an effort to introduce the terminology used
throughout this User’s Guide, as shown in Figure 1.
NB: This particular representation is not intended to represent all possible testbench architectures or every
type use of UVM in the electronic design automation (EDA) industry.
UVM Testbench
UVM Test
Sequences
UVM Environment
Config/Factory
Overrides
UVM
Sequencer
UVM Agent
UVM
Scoreboard
UVM Agent
UVM
Environment
UVM
Environment
Design
Under Test
(DUT)
Figure 1—Typical UVM Testbench Architecture
Copyright © 2011 - 2015 Accellera. All rights reserved.
1
October 8, 2015
UVM 1.2 User’s Guide
1.1.1 UVM Testbench
The UVM Testbench typically instantiates the Design under Test (DUT) module and the UVM Test class,
and configures the connections between them. If the verification collaterals include module-based
components, they are instantiated under the UVM Testbench as well. The UVM Test is dynamically
instantiated at run-time, allowing the UVM Testbench to be compiled once and run with many different
tests.
Note that in some architectures, the Testbench term is used to refer to a special module that encapsulates
verification collaterals only, which in turn are integrated up with the DUT.
1.1.2 UVM Test
The UVM Test is the top-level UVM Component in the UVM Testbench. The UVM Test typically performs
three main functions: Instantiates the top-level environment, configures the environment (via factory
overrides or the configuration database), and applies stimulus by invoking UVM Sequences through the
environment to the DUT.
Typically, there is one base UVM Test with the UVM Environment instantiation and other common items.
Then, other individual tests will extend this base test and configure the environment differently or select
different sequences to run.
1.1.3 UVM Environment
The UVM Environment is a hierarchical component that groups together other verification components that
are interrelated. Typical components that are usually instantiated inside the UVM Environment are UVM
Agents, UVM Scoreboards, or even other UVM Environments. The top-level UVM Environment
encapsulates all the verification components targeting the DUT.
For example: In a typical system on a chip (SoC) UVM Environment, you will find one UVM Environment
per IP (e.g., PCIe Environment, USB Environment, Memory Controller Environment, etc.). Sometimes,
those IP Environments are grouped together into Cluster Environments (e.g., IO Environment, Processor
Environment, etc.) that are grouped together eventually in the to- level SoC Environment.
1.1.4 UVM Scoreboard
The UVM Scoreboard’s main function is to check the behavior of a certain DUT. The UVM Scoreboard
usually receives transactions carrying inputs and outputs of the DUT through UVM Agent analysis ports
(connections are not depicted in Figure 1), runs the input transactions through some kind of a reference
model (also known as the predictor) to produce expected transactions, and then compares the expected
output versus the actual output.
There are different methodologies on how to implement the scoreboard, the nature of the reference model,
and how to communicate between the scoreboard and the rest of the testbench.
1.1.5 UVM Agent
The UVM Agent is a hierarchical component that groups together other verification components that are
dealing with a specific DUT interface (see Figure 2). A typical UVM Agent includes a UVM Sequencer to
manage stimulus flow, a UVM Driver to apply stimulus on the DUT interface, and a UVM Monitor to
2
Copyright © 2011 - 2015 Accellera. All rights reserved.
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