华为畅玩8A 原理图电路图.pdf-资料库

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1 2 3 4 5 6 59.GPS 60.WIFI/BT BB 61.WIFI/BT RF 62.Reserved 63.NFC 64.RESERVED 65.RESERVED 66.ANT Match 67.MAIN ANT Tuner 68.NFC_BB 69.Reserved AP SCHEMETIC 1. Index 2. MT6357 Control 3. MT6371 Charger 4. MT6371 POWER/Contrl 5. MT6357 Buck 6. MT6357 LDO 7. MT6357 Codec 8. MT6762 Control 9. MT6762 EBIF MIPI 10. MT6762 GPIO 11. MT6762 RF IF. 12. MT6762 Power1 13. MT6762 Power2 14. Ext_BUCK/LDO 15. eMMC and LPDDR3 16. Battery/Micro USB Connector 17. Speaker and Vibrator 18. MIC and Receiver 19. Earphone 20. LCD interface and backlight driver 21. Main/Slave Camera and Flash LED 22. Sensor 23. SIM/TF card 24. Keypad/LED/Status indicator 25. Flash LED 26. RESERVED 27. RESERVED 28. RESERVED 29. Subconnector 30. Test Points/Shields A B C D 31.RF Interface 32.RESERVED 33.Main Antenna Switcher 34.RESERVED 35.RESERVED 36.RESERVED 37.QFE2320(MMPA) 38.Circuit of MMPA 39.TRX_B1 40.TRX_B8 41.TRX_B5 42.TRX_B3/GSM1900 43.RESERVED 44.RESERVED 45.DRX LNA B3/B26 46.RESERVED 47.TRX_B41 48.RESERVED 49.RESERVED 50.RESERVED 51.DRX LNA B41/B1 52.DRX_B1/B3/B26 53.RESERVED 54.DRX_B41 55.DRX_ANT_SWITCH 56.WTR4905 57.RESERVED 58.ET_APT A B C D _SCHZH 1 2 3 4 5 6

1 2 3 4 5 6 2. MT6357 Control TP202 D201 1 PWRKEY HOMEKEY SYSRSTB WATCHDOG R201 2 PWRKEY_PMIC UVLO_VTH SRCLKENA0 SRCLKENA1 TP201 EXT_PMIC_EN2 PWRAP_SPI0_CSN PWRAP_SPI0_CK PWRAP_SPI0_MO PWRAP_SPI0_MI R4 PWRKEY N4 R5 T8 N3 FCHR_ENB RESETB WDTRSTB_IN UVLO_VTH N7 N8 M5 N5 M6 R8 M8 M7 M9 P5 P9 SRCLKEN_IN0 SRCLKEN_IN1 EXT_PMIC_EN1 EXT_PMIC_EN2 EXT_PMIC_PG SPI_CSN SPI_CLK SPI_MOSI SPI_MISO PMU_TESTMODE FSOURCE U201 MT6357 5 f o 1 e c a f r e t n I L R T C VRTC28 RTC32K_1V8_0 RTC32K_1V8_1 RTC32K_2V8 AVSS22_XO AVSS22_XOBUF1 AVSS22_XOBUF2 AVSS22_XO_ISO_1 AVSS22_XO_ISO_2 XO_SOC XO_CEL XO_WCN XO_NFC XO_EXT XTAL1 XTAL2 AVDD18_AUXADC AVSS18_AUXADC AUXADC_VIN R12 P14 R15 P11 M2 P1 R1 N2 P2 R3 T1 P3 R2 T2 M1 N1 R7 P7 T7 C202 close to PMIC VRTC28 C202 RTC32K_CK SG201S G S SG202S G S SG203S G S PMIC_CLK_BB PMIC_CLK_RF PMIC_CLK_WCN PMIC_CLK_NFC C203 C201 C208 BOM note:NO NFC C208 DNI XTAL1 XTAL2 C204 VAUX18_PMU CAD Note:Protect VAUX18_PMU net! AVSS18_AUXADC SG204S G S C205 AUXADC_IN Route AUXADC_IN differentail with AVDD18_AUXADC AVSS18_AUXADC X201 2 1 1 2 C 0 1 2 C 9 0 2 C XTAL1 1 SG205 SG206 SG207 VSYS VSYS VBAT BATON VBUS_USB_IN R209 SG SG SG S S S R211 2 1 2 C 0 1 2 R VCDT CHRLDO N9 VSYSSNS M13 BATSNS N13 ISENSE R13 BATON T11 VCDT U201 MT6357 CHG_DM CHG_DP PCHR_LED R11 P13 CHRLDO CHG Interface 2 of 5 VDRV CS_P CS_N ISINK1 M10 M11 N12 T10 R10 L12 CHD_DM CHD_DP CS_P CS_N Route differential Route differential / D N G T U O H T - N I - H T 4 3 XTAL2 26MHZ SMT2520 VAUX18_PMU R203 AUXADC_IN A B C D A B C D _SCHZH 1 2 3 4 5 6

1 2 3 4 5 6 3. MT6371 Charger PWRKEY R304 E8 CHG_QONB WATCHDOG EINT_CHG_0 GPIO_CHG_EN_0 H8 J6 B8 E9 D8 F8 MRSTB IRQB PD_IRQB CHG_ENB CHG_OTG CHG_DSEL A5 A4 D+ D- SCL5 SDA5 J8 J9 SCL SDA BL_VDDA DB_VDDA C10 K10 VDDM VDDA K9 J10 AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 AGND7 AGND8 AGND9 AGND10 E5 E6 E7 F5 F6 F7 G5 G6 G7 G9 U301 MT6371 3 f o 1 e c a f r e t n I 1 C S I M PWR_SUBPMIC_VDDA 1 1 3 C 2 1 3 C 4 1 3 C AGND SG304 S G S A B C D E4 OVP_CTRL F4 NC VBUS_USB_IN 5 0 3 C SG305 S G S PGND GND A1 A2 A3 D1 D2 D3 E2 CHG_VIN1 CHG_VIN2 CHG_VIN3 CHG_PGND1 CHG_PGND2 CHG_PGND3 VBUS B9 PD_VCONN5V C9 A9 PD_CC1 PD_CC2 Close CHG_ILIM C8 CHG_ILIM G4 CHG_STAT 5 0 3 R CHG_VMID1 CHG_VMID2 CHG_VMID3 VBAT1 VBAT2 VBAT3 VBAT4 VBATS CHG_BOOT CHG_VLX1 CHG_VLX2 CHG_VLX3 VSYS1 VSYS2 VSYS3 CHG_VDDP CHG_VBATOVPB B1 B2 B3 G1 G2 H1 H2 D5 D4 C1 C2 C3 F1 F2 E1 E3 F3 U301 MT6371 3 f o 2 e c a f r e t n I 2 C S I M PWR_SUBPMIC_VCHG_VMID 6 0 3 C PGND SG301 S G S VBAT PWR_SUBPMIC_VBATS C308 L301 VSYS 9 0 3 C CHG_VDDP C310 J3 TS BAT_ID A B C D _SCHZH 1 2 3 4 5 6

1 2 3 4 5 6 4. MT6371 POWER/Contrl VSYS FP_MT6371_VCC 3 1 4 C 4 1 4 C J2 LDO_VIN J1 LDO_VOUT CHG_LED_BLUE CHG_LED_GREEN CHG_LED_RED H5 J5 J4 H4 RGB_ISINK1 RGB_ISINK2 RGB_ISINK3 RGB_ISINK4 U301 MT6371 3 f o 3 e c a f r e t n I 3 C S I M FL_VINTORCH FL_LEDCS1 FL_LEDCS2 FL_VMID1 FL_VMID2 FL_VMID3 FL_TORCH FL_STROBE FL_TXMASK C6 A7 A6 B4 B5 B6 D7 D6 G8 VSYS FLASH_MAIN_LED FLASH_FRONT_LED PWR_SUBPMIC_VCHG_VMID 2 1 4 C 5 1 4 C GND PGND S SG SG401 BL_VLX A10 PWR_SUBPMIC_BL_VLX L401 VSYS BL_VOUT D9 BL_PGND B10 1 0 4 C BL_LED1 BL_LED2 BL_LED3 BL_LED4 D10 E10 LCM_LEDK_1 LCM_LEDK_2 LCM_LEDK_3 F10 G10 BL_PWM H9 BL_EN H10 GND 2 1 0 4 D 1 R461 1 2 0 4 C 2 LCM_LEDA 3 0 4 C BL_PGND SG402 SG S DISP_PWM VSYS L402 DB_PGND SG403 SG S 8 0 4 C GND 2 LCM_AVDD 1 R462 9 0 4 C DB_POSVLX DB_POSPGND DB_POSVOUT DB_BSTVOUT DB_NEGCF1 DB_NEGCF2 DB_NEGVOUT DB_NEGPGND DB_ENN DB_ENP COMPONENT_HIGH_MAX=0.6MM K7 K8 K5 K6 C410 K4 C411 K2 K1 K3 H6 H7 R463 1 2 LCM_AVEE 4 0 4 C SG404 SG S A B C D A B C D _SCHZH 1 2 3 4 5 6

1 2 3 4 5 6 5. MT6357 Buck VSYS For EOS 1 2 1 0 5 D 3 1 5 C A B C D R501 Must SMT R501 C501 SG501 SG S C512 SG502 SG S C503 SG503 SG S C504 SG504 SG S C505 SG505 SG SG506 SG C506 S S B2 B1 A4 B4 C4 A5 B5 C5 A8 B8 C8 C9 B9 A13 B13 A12 B12 C12 A2 A3 B3 B14 A14 A15 B15 VSYS_SMPS GND_SMPS VSYS_VPROC1 VSYS_VPROC2 VSYS_VPROC3 GND_VPROC1 GND_VPROC2 GND_VPROC3 VSYS_VCORE1 VSYS_VCORE2 VSYS_VCORE3 GND_VCORE1 GND_VCORE2 VSYS_VMODEM1 VSYS_VMODEM2 GND_VMODEM1 GND_VMODEM2 GND_VMODEM3 VSYS_VPA1 VSYS_VPA2 GND_VPA VSYS_VS1_1 VSYS_VS1_2 GND_VS1_1 GND_VS1_2 U201 MT6357 5 f o 4 e c a f r e t n I 1 R W P VPROC1 VPROC2 VPROC3 VPROC4 VPROC5 VPROC6 VPROC_FB GND_VPROC_FB VCORE1 VCORE2 VCORE3 VCORE4 VCORE_FB GND_VCORE_FB VMODEM1 VMODEM2 VMODEM_FB GND_VMODEM_FB VPA VPA_FB VS1_1 VS1_2 VS1_FB A6 A7 B6 B7 C6 C7 C2 D2 A9 A10 B10 C10 D3 E3 B11 C11 E13 D14 A1 E4 A16 B16 E14 L501 DVDD_DVFS The max current of DCDD_CORE is 5A DVDD_DVFS DVDD_DVFS_GND L502 Route differential and shielding Sense from PND cap near SOC The max current of DCDD_DVFS is 4.21A DVDD_CORE DVDD_CORE DVDD_CORE_GND VMODEM L503 Route differential and shielding Sense from PND cap near SOC The max current of DVDD_MODEM is 4A DVDD_MODEM DVDD_MODEM_6357_FB DVDD_MODEM_6357_GND Route differential and shielding L504 VPA_PMU_FB SG507 SG S L505 The max current of VS1 is 3.3A VS1_PMU VS1_PMU_FB VPA_PMU 0 1 5 C A B C D _SCHZH 1 2 3 4 5 6

A B C D 1 2 3 4 5 6 6. MT6357 LDO R602 R601 SG606 SG S SG607 SG S Suggest trace width > 40 mil VS2_PMU VS1_PMU EXT_VS2 EXT_VS2_FB VS1_PMU VS1_PMU_FB SG608 SG S VS2_PMU VSYS For EOS 7 3 6 C 2 0 6 C 3 0 6 C 1 0 6 C 8 3 6 C 4 0 6 C 5 0 6 C 6 0 6 C All LDO inout Caps close to PMIC C607&SG601 Close to PMIC SG601 SG S VIO18_PMU SG604 SG S C607 C608 C17 F15 F17 G14 N17 K7 F13 G8 G7 G9 G12 H6 G10 G11 H7 H8 H9 H10 H11 F12 F11 F10 F9 H12 J6 D7 D8 D6 D9 F5 J7 D10 D11 D12 D13 F6 J8 K12 E6 E7 E8 F7 J9 E11 E9 E10 E12 F8 J11 T14 T13 DVDD18_DIG K10 L10 VS1_LDO1 VS2_LDO1 VS2_LDO2 VSYS_LDO1 VSYS_LDO2 VSYS_LDO3 D_GND1 D_GND2 D_GND3 D_GND4 D_GND5 D_GND6 D_GND7 D_GND8 D_GND9 D_GND10 D_GND11 D_GND12 D_GND13 D_GND14 D_GND15 D_GND16 D_GND17 D_GND18 D_GND19 D_GND20 D_GND21 D_GND22 D_GND23 D_GND24 D_GND25 D_GND26 D_GND27 D_GND28 D_GND29 D_GND30 D_GND31 D_GND32 D_GND33 D_GND34 D_GND35 D_GND36 D_GND37 D_GND38 D_GND39 D_GND40 D_GND41 D_GND42 D_GND43 VREF GND_VREF DVDD18_IO DVDD18_DIG U201 MT6357 5 f o 4 e c a f r e t n I 2 R W P VFE28 VXO22 VCN28 VCAMA VAUX18 VAUD28 VCN33 VLDO28 VIO28 VMC VMCH VEMC VSIM1 VSIM2 VIBR VUSB VEFUSE L14 T4 K13 H16 T5 L7 P17 L16 K15 L15 N16 L17 J17 K16 M16 J14 H15 VRF18 D16 VCN18 VCAMD VCAMIO VIO18 E15 E17 A17 B17 VRF12 E16 VFE28_PMU VXO22_PMU VCN28_PMU VCAMA_PMU VAUX18_PMU VAUD28_PMU VCN33_PMU VLDO28_PMU VIO28_PMU VMC_PMU VMCH_PMU VEMC_PMU VSIM1_PMU VSIM2_PMU VIBR_PMU VEFUSE_PMU VRF18_PMU VCN18_PMU VCAMD_PMU VCAMIO_PMU VIO18_PMU VRF12_PMU VUSB_PMU VSRAM_PROC VSRAM_OTHERS VDRAM TREF G15 G16 H17 R9 DVDD_SRAM_DVFS VSRAM_OTHERS_PMU VDRAM_PMU TREF_PMU CAD Note:TREF need protect. C611 C612 C613 C614 C615 C616 C617 C618 C619 C620 C621 C622 C623 C624 C625 C626 C627 C628 C629 C630 C631 C632 SG605 SG SG603 SG S S AVDD18_SOC EMI_VDD1 Output Voltage(V) Imax(mA) Cap range NAME VFE28 VXO22 VRF18 VRF12 2.8 2.24 1.81 1.2 VEFUSE 1.2/1.3/1.5/1.8/2.0/2.8/3.0/3.3 VCN33 VCN28 VCN18 VCAMA VCAMD 3.3/3.4/3.5/3.6 2.8 1.8 1.8/2.5/2.7/2.8/2.9/2.95/3 1/1.05/1.1/1.2/1.3/1.5/1.8 VCAMIO 1.8 VLDO28 2.8/3.0 VAUX18 VAUD28 VIO28 VIO18 1.8 2.8 2.8 1.8 VSRAM_PROC 0.75--1.31(1.25) VSRAM_OTHERS 0.75---1.3(1.25) 40 25 450 200 200 400 40 200 145 350(<=1.5) 200(1.8) 140 1---2.2 2.2--2.3 9.4--10.4 1---2.2 1---2.2 1---1.47 1---2.2 1---2.2 1---11 1---5.7 1---4 360 1---7.7 20 50 200 600 130 200 1---2.2 1---2.2 1---4 4.7-21 2.2--3.61 2.2--3.61 C633 C634 C635 C636 VMC VMCH VEMC VSIM1 VSIM2 VIBR VUSB VDRAM 1.12/1.24 1200 4.7--44 1.86/2.9/3.0/3.3 2.9/3.0/3.3 2.9/3.0/3.3 1.7/1.8/1.86/2.76/3.0/3.1 1.7/1.8/1.86/2.76/3.0/3.1 200 800 400 50 50 1---2.2 1---5.9 1---5.9 1---2.2 1---2.2 1.2/1.3/1.5/1.8/2.0/2.8/3.0/3.3 200 1---2.2 3.07 VRTC28 2.8 DVDD18_DIG 1.8 50 2 10 1---2.2 Near end:0.1uF Far:1.5K+super Cap 1 A B C J10 DVSS18_IO 9 0 6 C 0 1 6 C SG602 SG S 1 2 3 4 5 6 D _SCHZH

1 2 3 4 5 6 7. MT6357 Codec AUD_CLK_MISO AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_SYNC_MISO AUD_CLK_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_SYNC_MOSI AU_VIN0_P AU_VIN0_N AU_VIN1_P AU_VIN1_N AU_VIN2_P AU_VIN2_N ACCDET HP_EINT AU_HSP AU_HSN AU_HPL AU_REFN AU_HPR 1 0 7 C C701 close to PMIC Caps close to PMIC AVDD28_AUD AVSS28_AUD AU_MICBIAS0 AU_MICBIAS1 AVDD18_AUD AVSS18_AUD AU_V18N FLYP FLYN K1 H5 L3 M3 G2 F2 D1 F1 E2 C702 C703 C704 C705 C706 C707 R16 AUD_CLK_MISO T17 AUD_DAT_MISO0 R17 AUD_DAT_MISO1 T16 AUD_SYNC_MISO P16 P15 N14 M14 AUD_CLK_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_SYNC_MOSI K3 K4 K5 L5 J4 J5 M4 J1 J2 H3 G3 F4 F3 G6 G5 AU_VIN0_P AU_VIN0_N AU_VIN1_P AU_VIN1_N AU_VIN2_P AU_VIN2_N ACCDET HP_EINT AU_HPL AU_REFN AU_HPR AU_LOLP AU_LOLN AU_HSP AU_HSN U201 MT6357 5 f o 3 e c a f r e t n I O I D U A VAUD28_PMU AVSS28_AUD S G S SG701 AU_MICBIAS0 AU_MICBIAS1 VIO18_PMU SG702 S G S Notice: 1. AVSS18_AUD connect to GND with very short trace 2. AU_V18N & avdd18_aud to caps route 6mil . A B C D A B C D _SCHZH 1 2 3 4 5 6

1 2 3 4 5 6 8. MT6762 Control A B C D SYSRSTB WATCHDOG SRCLKENA0 SRCLKENA1 RTC32K_CK E27 SYSRSTB K24 L25 M25 H26 WATCHDOG SRCLKENA0 SRCLKENA1 RTC32K_CK PWRAP_SPI0_CSN PWRAP_SPI0_CK PWRAP_SPI0_MO PWRAP_SPI0_MI K27 L27 M27 K28 PWRAP_SPI0_CSN PWRAP_SPI0_CK PWRAP_SPI0_MO PWRAP_SPI0_MI AUD_CLK_MOSI AUD_CLK_MISO AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_SYNC_MISO AUD_SYNC_MOSI J25 G27 J27 J28 K26 K25 H27 J26 AUD_CLK_MOSI AUD_CLK_MISO AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_SYNC_MISO AUD_SYNC_MOSI U801 MT6762 9 f o 5 e c a f r e t n I L R T C TESTMODE TP_PLLGP TN_PLLGP CDM3P5A CDM5P5A F27 W13 W12 AC5 AB6 A1 A28 AG1 AG28 NC1 NC2 NC3 NC4 MSDC0_DAT7 MSDC0_DAT6 MSDC0_DAT5 MSDC0_DAT4 MSDC0_DAT3 MSDC0_DAT2 MSDC0_DAT1 MSDC0_DAT0 MSDC0_RSTB MSDC0_CMD MSDC0_CLK MSDC0_DSL A26 B24 B23 A23 C24 A25 D24 C26 C25 B25 D25 B26 MSDC0_DAT7 MSDC0_DAT6 MSDC0_DAT5 MSDC0_DAT4 MSDC0_DAT3 MSDC0_DAT2 MSDC0_DAT1 MSDC0_DAT0 MSDC0_RSTB MSDC0_CMD MSDC0_CLK MSDC0_DSL TP801 TP804 TP802 TP803 AP JTAG:CS LO,MOSI LO. Default:No JTAG modem. BOM SMT as Value PWRAP_SPI0_CSN PWRAP_SPI0_MI 5 0 8 R 2 0 8 R A B C D _SCHZH 1 2 3 4 5 6

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华为畅玩8A 原理图电路图.pdf

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