Num*(2^15)ans = Columns 1 through 10 10090 1945 >> Num -0.0981 Num = 0.0594 -3213 -3844 1217 14618 10090 -0.1173 0.0371 0.3079 1217 0.4461 -3844 0.3079 -3213 Column 11 1945 0.0371 -0.1173 -0.0981 0.0594 >> 

// Module: filter // // Generated by MATLAB(R) 7.5 and the Filter Design HDL Coder 2.1. // // Generated on: 2008-11-14 04:56:30 // // ------------------------------------------------------------- // ------------------------------------------------------------- // HDL Code Generation Options: // // TargetDirectory: H:\work\MATLAB\wqfir_VerilogHDL // TargetLanguage: verilog // TestBenchName: fir_test_1113 // TestBenchStimulus: chirp impulse noise ramp step // LoopUnrolling: on // // Filter Settings: // // Discrete-Time FIR Filter (real) // ------------------------------- // Filter Structure // Filter Length // Stable // Linear Phase // Arithmetic // Numerator // Input // Filter Internals Output // // Product determined) // : Yes : Yes (Type 1) : fixed : s16,15 -> [-1 1) : s16,15 -> [-1 1) : Direct-Form FIR : 11 : s32,30 -> [-2 2) : Full Precision Accumulator : s32,30 -> [-2 2) (auto determined) (auto determined) : s30,30 -> [-5.000000e-001 5.000000e-001) Round Mode Overflow Mode // // // ------------------------------------------------------------- : No rounding : No overflow `timescale 1 ns / 1 ns module filter ( clk, clk_enable, reset, filter_in, filter_out ); input input input input output clk; clk_enable; reset; signed [15:0] filter_in; //sfix16_En15 signed [31:0] filter_out; //sfix32_En30 // Local Functions // Type Definitions // Constants parameter signed [15:0] coeff1 = 16'b0000011110011001; //sfix16_En15 parameter signed [15:0] coeff2 = 16'b1111001101110011; //sfix16_En15 parameter signed [15:0] coeff3 = 16'b1111000011111100; //sfix16_En15 parameter signed [15:0] coeff4 = 16'b0000010011000001; //sfix16_En15 parameter signed [15:0] coeff5 = 16'b0010011101101010; //sfix16_En15 parameter signed [15:0] coeff6 = 16'b0011100100011010; //sfix16_En15 parameter signed [15:0] coeff7 = 16'b0010011101101010; //sfix16_En15 parameter signed [15:0] coeff8 = 16'b0000010011000001; //sfix16_En15 parameter signed [15:0] coeff9 = 16'b1111000011111100; //sfix16_En15 parameter signed [15:0] coeff10 = 16'b1111001101110011; //sfix16_En15 (auto 

parameter signed [15:0] coeff11 = 16'b0000011110011001; //sfix16_En15 signed [15:0] delay_pipeline [0:10] ; // sfix16_En15 // Signals reg wire signed [29:0] product11; // sfix30_En30 wire signed [31:0] mul_temp; // sfix32_En30 wire signed [29:0] product10; // sfix30_En30 wire signed [31:0] mul_temp_1; // sfix32_En30 wire signed [29:0] product9; // sfix30_En30 wire signed [31:0] mul_temp_2; // sfix32_En30 wire signed [29:0] product8; // sfix30_En30 wire signed [31:0] mul_temp_3; // sfix32_En30 wire signed [29:0] product7; // sfix30_En30 wire signed [31:0] mul_temp_4; // sfix32_En30 wire signed [29:0] product6; // sfix30_En30 wire signed [31:0] mul_temp_5; // sfix32_En30 wire signed [29:0] product5; // sfix30_En30 wire signed [31:0] mul_temp_6; // sfix32_En30 wire signed [29:0] product4; // sfix30_En30 wire signed [31:0] mul_temp_7; // sfix32_En30 wire signed [29:0] product3; // sfix30_En30 wire signed [31:0] mul_temp_8; // sfix32_En30 wire signed [29:0] product2; // sfix30_En30 wire signed [31:0] mul_temp_9; // sfix32_En30 wire signed [31:0] product1_cast; // sfix32_En30 wire signed [29:0] product1; // sfix30_En30 wire signed [31:0] mul_temp_10; // sfix32_En30 wire signed [31:0] sum1; // sfix32_En30 wire signed [31:0] add_signext; // sfix32_En30 wire signed [31:0] add_signext_1; // sfix32_En30 wire signed [32:0] add_temp; // sfix33_En30 wire signed [31:0] sum2; // sfix32_En30 wire signed [31:0] add_signext_2; // sfix32_En30 wire signed [31:0] add_signext_3; // sfix32_En30 wire signed [32:0] add_temp_1; // sfix33_En30 wire signed [31:0] sum3; // sfix32_En30 wire signed [31:0] add_signext_4; // sfix32_En30 wire signed [31:0] add_signext_5; // sfix32_En30 wire signed [32:0] add_temp_2; // sfix33_En30 wire signed [31:0] sum4; // sfix32_En30 wire signed [31:0] add_signext_6; // sfix32_En30 wire signed [31:0] add_signext_7; // sfix32_En30 wire signed [32:0] add_temp_3; // sfix33_En30 wire signed [31:0] sum5; // sfix32_En30 wire signed [31:0] add_signext_8; // sfix32_En30 wire signed [31:0] add_signext_9; // sfix32_En30 wire signed [32:0] add_temp_4; // sfix33_En30 wire signed [31:0] sum6; // sfix32_En30 wire signed [31:0] add_signext_10; // sfix32_En30 wire signed [31:0] add_signext_11; // sfix32_En30 wire signed [32:0] add_temp_5; // sfix33_En30 wire signed [31:0] sum7; // sfix32_En30 wire signed [31:0] add_signext_12; // sfix32_En30 wire signed [31:0] add_signext_13; // sfix32_En30 wire signed [32:0] add_temp_6; // sfix33_En30 wire signed [31:0] sum8; // sfix32_En30 wire signed [31:0] add_signext_14; // sfix32_En30 wire signed [31:0] add_signext_15; // sfix32_En30 wire signed [32:0] add_temp_7; // sfix33_En30 wire signed [31:0] sum9; // sfix32_En30 wire signed [31:0] add_signext_16; // sfix32_En30 wire signed [31:0] add_signext_17; // sfix32_En30 wire signed [32:0] add_temp_8; // sfix33_En30 wire signed [31:0] sum10; // sfix32_En30 wire signed [31:0] add_signext_18; // sfix32_En30 wire signed [31:0] add_signext_19; // sfix32_En30 wire signed [32:0] add_temp_9; // sfix33_En30 reg signed [31:0] output_register; // sfix32_En30 

// Block Statements always @( posedge clk or posedge reset) begin: Delay_Pipeline_process if (reset == 1'b1) begin delay_pipeline[0] <= 0; delay_pipeline[1] <= 0; delay_pipeline[2] <= 0; delay_pipeline[3] <= 0; delay_pipeline[4] <= 0; delay_pipeline[5] <= 0; delay_pipeline[6] <= 0; delay_pipeline[7] <= 0; delay_pipeline[8] <= 0; delay_pipeline[9] <= 0; delay_pipeline[10] <= 0; end else begin if (clk_enable == 1'b1) begin delay_pipeline[0] <= filter_in; delay_pipeline[1] <= delay_pipeline[0]; delay_pipeline[2] <= delay_pipeline[1]; delay_pipeline[3] <= delay_pipeline[2]; delay_pipeline[4] <= delay_pipeline[3]; delay_pipeline[5] <= delay_pipeline[4]; delay_pipeline[6] <= delay_pipeline[5]; delay_pipeline[7] <= delay_pipeline[6]; delay_pipeline[8] <= delay_pipeline[7]; delay_pipeline[9] <= delay_pipeline[8]; delay_pipeline[10] <= delay_pipeline[9]; end end end // Delay_Pipeline_process assign mul_temp = delay_pipeline[10] * coeff11; assign product11 = mul_temp[29:0]; assign mul_temp_1 = delay_pipeline[9] * coeff10; assign product10 = mul_temp_1[29:0]; assign mul_temp_2 = delay_pipeline[8] * coeff9; assign product9 = mul_temp_2[29:0]; assign mul_temp_3 = delay_pipeline[7] * coeff8; assign product8 = mul_temp_3[29:0]; assign mul_temp_4 = delay_pipeline[6] * coeff7; assign product7 = mul_temp_4[29:0]; assign mul_temp_5 = delay_pipeline[5] * coeff6; assign product6 = mul_temp_5[29:0]; assign mul_temp_6 = delay_pipeline[4] * coeff5; assign product5 = mul_temp_6[29:0]; assign mul_temp_7 = delay_pipeline[3] * coeff4; assign product4 = mul_temp_7[29:0]; assign mul_temp_8 = delay_pipeline[2] * coeff3; assign product3 = mul_temp_8[29:0]; assign mul_temp_9 = delay_pipeline[1] * coeff2; assign product2 = mul_temp_9[29:0]; assign product1_cast = $signed({{2{product1[29]}}, product1}); assign mul_temp_10 = delay_pipeline[0] * coeff1; 

assign product1 = mul_temp_10[29:0]; assign add_signext = product1_cast; assign add_signext_1 = $signed({{2{product2[29]}}, product2}); assign add_temp = add_signext + add_signext_1; assign sum1 = add_temp[31:0]; assign add_signext_2 = sum1; assign add_signext_3 = $signed({{2{product3[29]}}, product3}); assign add_temp_1 = add_signext_2 + add_signext_3; assign sum2 = add_temp_1[31:0]; assign add_signext_4 = sum2; assign add_signext_5 = $signed({{2{product4[29]}}, product4}); assign add_temp_2 = add_signext_4 + add_signext_5; assign sum3 = add_temp_2[31:0]; assign add_signext_6 = sum3; assign add_signext_7 = $signed({{2{product5[29]}}, product5}); assign add_temp_3 = add_signext_6 + add_signext_7; assign sum4 = add_temp_3[31:0]; assign add_signext_8 = sum4; assign add_signext_9 = $signed({{2{product6[29]}}, product6}); assign add_temp_4 = add_signext_8 + add_signext_9; assign sum5 = add_temp_4[31:0]; assign add_signext_10 = sum5; assign add_signext_11 = $signed({{2{product7[29]}}, product7}); assign add_temp_5 = add_signext_10 + add_signext_11; assign sum6 = add_temp_5[31:0]; assign add_signext_12 = sum6; assign add_signext_13 = $signed({{2{product8[29]}}, product8}); assign add_temp_6 = add_signext_12 + add_signext_13; assign sum7 = add_temp_6[31:0]; assign add_signext_14 = sum7; assign add_signext_15 = $signed({{2{product9[29]}}, product9}); assign add_temp_7 = add_signext_14 + add_signext_15; assign sum8 = add_temp_7[31:0]; assign add_signext_16 = sum8; assign add_signext_17 = $signed({{2{product10[29]}}, product10}); assign add_temp_8 = add_signext_16 + add_signext_17; assign sum9 = add_temp_8[31:0]; assign add_signext_18 = sum9; assign add_signext_19 = $signed({{2{product11[29]}}, product11}); assign add_temp_9 = add_signext_18 + add_signext_19; assign sum10 = add_temp_9[31:0]; always @ (posedge clk or posedge reset) begin: Output_Register_process if (reset == 1'b1) begin output_register <= 0; end else begin if (clk_enable == 1'b1) begin output_register <= sum10; end end end // Output_Register_process // Assignment Statements assign filter_out = output_register; endmodule // filter