cadence综合工具RTL_Compiler用户手册.pdf

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Contents

Preface

About This Manual

Additional References

How to Use the Documentation Set

Reporting Problems or Errors in Manuals

Customer Support

Cadence Online Support

Other Support Offerings

Messages

Man Pages

Command-Line Help

Getting the Syntax for a Command

Getting the Syntax for an Attribute

Searching for Attributes

Searching For Commands When You Are Unsure of the Name

Documentation Conventions

Text Command Syntax

Introduction

Overview

The CDN_SYNTH_ROOT Variable

Using the .synth_init Initialization File

Working in the RTL Compiler Shell

Navigation

Objects and Attributes

Output Redirection

Scripting

Using SDC Interactively

Getting Help

Help Command

The -help Option

RTL Compiler Messages: Errors, Warnings, and Information

RTL Compiler Design Information Hierarchy

Overview

Setting the Current Design

Specifying Hierarchy Names

Describing the Design Information Hierarchy

Working in the Top-Level (root) Directory

Working in the Designs Hierarchy

Working in the Library Directory

Working in the hdl_libraries Directory

Working in the object_types Directory

Manipulating Objects in the Design Information Hierarchy

Ungrouping Modules During and After Elaboration

Finding Information in the Design Information Hierarchy

Using the cd Command to Navigate the Design Information Hierarchy

Using the ls Command to List Directory Objects and Attributes

Using the find Command to Search for Information

Using the get_attribute Command to Search for Information

Navigating a Sample Design

Tips and Shortcuts

Accessing UNIX Environment Variables from RTL Compiler

Working with Tcl in RTL Compiler

Using Command Line Keyboard Shortcuts

Using Command Abbreviations

Using Command Completion with the Tab Key

Using Wildcards

Using Smart Searches

Saving the Design Information Hierarchy

Using the Libraries

Overview

Tasks

Specifying Explicit Search Paths

Specifying Implicit Search Paths

Setting the Target Technology Library

Preventing the Use of Specific Library Cells

Forcing the Use of Specific Library Cells

Working with Liberty Format Technology Libraries

Importing LEF Files

Specifying Capacitance Information

Loading Files

Overview

Tasks

Updating Scripts through Patching

Running Scripts

Reading HDL Files

Loading HDL Files

Specifying the HDL Language Mode

Specifying HDL Search Paths

Reading Verilog Files

Defining Verilog Macros

Reading VHDL Files

Specifying the VHDL Environment

Verifying VHDL Code Compliance with the LRM

Specifying Illegal Characters in VHDL

Showing the VHDL Logical Libraries

Using Arithmetic Packages From Other Vendors

Modifying the Case of VHDL Names

Reading Designs with Mixed Verilog and VHDL Files

Reading in Verilog Modules and VHDL Entities With Same Names

Using Case Sensitivity in Verilog/VHDL Mixed-Language Designs

Reading and Elaborating a Structural Netlist Design

Reading a Partially Structural Design

Keeping Track of Loaded HDL Files

Importing the Floorplan

Elaborating the Design

Overview

Tasks

Performing Elaboration

Specifying Top-Level Parameters or Generic Values

Specifying HDL Library Search Paths

Elaborating a Specified Module or Entity

Naming Individual Bits of Array and Record Ports and Registers

Naming Parameterized Modules

Keeping Track of the RTL Source Code

Grouping an Extra Level of Design Hierarchy

Applying Constraints

Overview

Tasks

Importing and Exporting SDC

Validating Timing Constraints

Applying Timing Constraints

Importing Physical Information

Applying Design Rule Constraints

Creating Ideal Objects

Defining Optimization Settings

Overview

Preserving Instances and Modules

Grouping and Ungrouping Objects

Grouping

Ungrouping

Partitioning

Setting Boundary Optimization

Mapping to Complex Sequential Cells

Deleting Unused Sequential Instances

Optimizing Total Negative Slack

Making DRC the Highest Priority

Creating Hard Regions

Deleting Buffers and Inverters Driven by Hard Regions

Preventing Boundary Optimization Through Hard Regions

Removing Assign Statements

Super-threading

Overview

Licensing Requirements

Tasks

Setting Super-threading Optimization

Performing Synthesis

Overview

RTL Optimization

Global Focus Mapping

Remapping

Incremental Optimization (IOPT)

Tasks

Synthesizing your Design

Synthesizing Submodules

Synthesizing Unresolved References

Re-synthesizing with a New Library (Technology Translation)

Setting Effort Levels

Writing a SDF File

Quality of Silicon Prediction

Generic Gates in a Generic Netlist

Generic Flop

Generic Latch

Generic Mux

Generic Dont-Care

Writing the Generic Netlist

Reading the Netlist

Retiming the Design

Overview

Retiming for Timing

Retiming for Area

Tasks

Retiming Using the Automatic Top-Down Retiming Flow

Manual Retiming (Block Level Retiming)

Incorporating Design for Test (DFT) and Low Power Features

Localizing Retiming Optimizations to Particular Subdesigns

Controlling Retiming Optimization

Retiming Registers with Asynchronous Set and Reset Signals

Identifying Retimed Logic

Retiming Multiple Clock Designs

Performing Functional Verification

Overview

Tasks

Writing Out dofiles for Formal Verification

Generating Reports

Overview

Tasks

Generating Timing Reports

Generating Area Reports

Summarizing Messages

Redirecting Reports

Customizing the report Command

Analyzing the Log File

Interfacing to Place and Route

Overview

Preparing the Netlist for Place and Route or Third-Party Tools

Changing Names

Naming Flops

Removing Assign Statements

Handling Bit Blasted Port Styles

Handling Bit-Blasted Constants

Generating Design and Session Information

Saving and Restoring a Session in RTL Compiler

Writing Out the Design Netlist

Writing SDC Constraints

Writing an SDF File

Modifying the Netlist

Overview

Connecting Pins, Ports, and Subports

Disconnecting Pins, Ports, and Subports

Creating New Instances

Overriding Preserved Modules

Creating Unique Parameter Names

Naming Generated Components

Changing the Instance Library Cell

IP Protection

Overview

NC-Protect Coupling

Protection Levels

Tasks

Encrypting Designs within RTL Compiler

Encrypting Designs outside RTL Compiler

Loading Encrypted Designs

Examining Protection Settings

Writing Encrypted Designs

Design Hierarchy and Uniquification

Simple Synthesis Template

Encrypting Libraries

Index

Using Encounter® RTL Compiler Product Version 9.1 April 2010

 2003-2010 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as speciﬁed in this permission statement, this publication may not be copied, reproduced, modiﬁed, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modiﬁed in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the beneﬁt of any other party, whether or not for consideration. Patents: Cadence Product Encounter™ RTL Compiler described in this document, is protected by U.S. Patents [5,892,687]; [6,470,486]; 6,772,398]; [6,772,399]; [6,807,651]; [6,832,357]; and [7,007,247] Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Using Encounter RTL Compiler Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 How to Use the Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reporting Problems or Errors in Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Cadence Online Support Other Support Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Getting the Syntax for a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Getting the Syntax for an Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Searching for Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Searching For Commands When You Are Unsure of the Name . . . . . . . . . . . . . . . . 17 Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Text Command Syntax 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The CDN_SYNTH_ROOT Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Using the .synth_init Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Working in the RTL Compiler Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Objects and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Output Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Using SDC Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Help Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 April 2010 3 Product Version 9.1

Using Encounter RTL Compiler The -help Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RTL Compiler Messages: Errors, Warnings, and Information . . . . . . . . . . . . . . . . . . . 9 Describing the Design Information Hierarchy 2 RTL Compiler Design Information Hierarchy . . . . . . . . . . . . . . . . . . 11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting the Current Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specifying Hierarchy Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Working in the Top-Level (root) Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Working in the Designs Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Working in the Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Working in the hdl_libraries Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Working in the object_types Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Manipulating Objects in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . 41 Ungrouping Modules During and After Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Finding Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . 44 Using the cd Command to Navigate the Design Information Hierarchy . . . . . . . . . . . 44 Using the ls Command to List Directory Objects and Attributes . . . . . . . . . . . . . . . . . 45 Using the ﬁnd Command to Search for Information . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Using the get_attribute Command to Search for Information . . . . . . . . . . . . . . . . . . . 49 Navigating a Sample Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Tips and Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . . 57 Accessing UNIX Environment Variables from RTL Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Working with Tcl in RTL Compiler Using Command Line Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Using Command Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Using Command Completion with the Tab Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Using Wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Using Smart Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Saving the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3 Using the Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 April 2010 4 Product Version 9.1

Using Encounter RTL Compiler Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Specifying Explicit Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Specifying Implicit Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Setting the Target Technology Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Preventing the Use of Speciﬁc Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Forcing the Use of Speciﬁc Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Working with Liberty Format Technology Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Importing LEF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Specifying Capacitance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Deﬁning Verilog Macros 4 Loading Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Updating Scripts through Patching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Running Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Reading HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Loading HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Specifying the HDL Language Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Specifying HDL Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Reading Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Reading VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Specifying the VHDL Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Verifying VHDL Code Compliance with the LRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Specifying Illegal Characters in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Showing the VHDL Logical Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Using Arithmetic Packages From Other Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Modifying the Case of VHDL Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Reading in Verilog Modules and VHDL Entities With Same Names . . . . . . . . . . . . . 96 Using Case Sensitivity in Verilog/VHDL Mixed-Language Designs . . . . . . . . . . . . . . 97 Reading and Elaborating a Structural Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Reading a Partially Structural Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Keeping Track of Loaded HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Reading Designs with Mixed Verilog and VHDL Files April 2010 5 Product Version 9.1

Using Encounter RTL Compiler Importing the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5 Elaborating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Performing Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Specifying Top-Level Parameters or Generic Values . . . . . . . . . . . . . . . . . . . . . . . . 104 Specifying HDL Library Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Elaborating a Speciﬁed Module or Entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Naming Individual Bits of Array and Record Ports and Registers . . . . . . . . . . . . . . 107 Naming Parameterized Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Keeping Track of the RTL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Grouping an Extra Level of Design Hierarchy 6 Applying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Importing and Exporting SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Validating Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Applying Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Importing Physical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Applying Design Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Creating Ideal Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7 Deﬁning Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Preserving Instances and Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Grouping and Ungrouping Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Ungrouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 April 2010 6 Product Version 9.1

Using Encounter RTL Compiler Setting Boundary Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Mapping to Complex Sequential Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Deleting Unused Sequential Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Optimizing Total Negative Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Making DRC the Highest Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Creating Hard Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Deleting Buffers and Inverters Driven by Hard Regions . . . . . . . . . . . . . . . . . . . . . . 157 Preventing Boundary Optimization Through Hard Regions . . . . . . . . . . . . . . . . . . . 158 Removing Assign Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8 Super-threading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Licensing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Setting Super-threading Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9 Performing Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 RTL Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Global Focus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Incremental Optimization (IOPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Synthesizing your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Synthesizing Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Synthesizing Unresolved References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Re-synthesizing with a New Library (Technology Translation) . . . . . . . . . . . . . . . . . 175 Setting Effort Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Writing a SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Quality of Silicon Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Generic Gates in a Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Generic Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Generic Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 April 2010 7 Product Version 9.1

Using Encounter RTL Compiler Generic Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Generic Dont-Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Writing the Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Reading the Netlist 10 Retiming the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Retiming for Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Retiming for Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Retiming Using the Automatic Top-Down Retiming Flow . . . . . . . . . . . . . . . . . . . . . 196 Manual Retiming (Block Level Retiming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Incorporating Design for Test (DFT) and Low Power Features . . . . . . . . . . . . . . . . . 200 Localizing Retiming Optimizations to Particular Subdesigns . . . . . . . . . . . . . . . . . . 202 Controlling Retiming Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Retiming Registers with Asynchronous Set and Reset Signals . . . . . . . . . . . . . . . . 204 Identifying Retimed Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Retiming Multiple Clock Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11 Performing Functional Veriﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Writing Out doﬁles for Formal Veriﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12 Generating Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Generating Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Generating Area Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Summarizing Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Redirecting Reports April 2010 8 Product Version 9.1

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