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88E1149 datasheet.pdf
Section 1. Signal Description
1.1 Pin Description
1.1.1 Pin Type Definitions
1.2 88E1149 176-Pin TQFP Package
1.3 88E1149 196-Pin TFBGA Package
Section 2. Functional Specifications
2.1 Copper Media Interface
2.2 MAC Interface
2.3 Loopback
2.3.1 MAC Interface Loopback
2.3.2 Line Loopback
2.3.3 External Loopback
2.4 Synchronizing FIFO
2.5 Copper Media Transmit and Receive Function
2.5.1 Transmit Side Network Interface
2.5.1.1 Multi-mode TX Digital to Analog Converter
2.5.1.2 Slew Rate Control and Waveshaping
2.5.2 Encoder
2.5.2.1 1000BASE-T
2.5.2.2 100BASE-TX
2.5.2.3 10BASE-T
2.5.3 Receive Side Network Interface
2.5.3.1 Analog to Digital Converter
2.5.3.2 Active Hybrid
2.5.3.3 Echo Canceller
2.5.3.4 NEXT Canceller
2.5.3.5 Baseline Wander Canceller
2.5.3.6 Digital Adaptive Equalizer
2.5.3.7 Digital Phase Lock Loop
2.5.3.8 Link Monitor
2.5.3.9 Signal Detection
2.5.4 Decoder
2.5.4.1 1000BASE-T
2.5.4.2 100BASE-TX
2.5.4.3 10BASE-T
2.6 Power Supplies
2.6.1 AVDDH
2.6.2 VDDC
2.6.3 AVDDT
2.6.4 DVDD
2.6.5 VDDO
2.6.6 Power Supply Sequencing
2.7 Power Management
2.7.1 Low Power Modes
2.7.2 Low Power Operating Modes
2.7.2.1 IEEE Power Down Mode
2.7.2.2 Energy Detect Power Down Modes
2.7.2.3 Energy Detect (Mode 1)
2.7.2.4 Energy Detect +TM (Mode 2)
2.7.2.5 Normal 10/100/1000 Mbps Operation
2.7.3 SGMII Effect on Low Power Modes
2.8 Auto-Negotiation
2.8.1 10/100/1000BASE-T Auto-Negotiation
2.8.2 SGMII Auto-Negotiation
2.8.2.1 Flow control Enhancement to SGMII Auto-Negotiation
2.8.2.2 Serial Interface Auto-Negotiation Bypass Mode
2.9 Downshift Feature
2.10 Virtual Cable Tester™ (VCT™)
2.11 Data Terminal Equipment (DTE) Detect
2.12 CRC Error Counter and Frame Counter
2.12.1 Enabling The CRC Error Counter and Frame Counter
2.13 Packet Generator
2.14 MDI/MDIX Crossover
2.15 Polarity Correction
2.16 LED
2.16.1 LED Polarity
2.16.2 Pulse Stretching and Blinking
2.16.3 Bi-Color LED Mixing
2.16.4 Modes of Operation
2.16.4.1 Compound LED Modes
2.16.4.2 Speed Blink
2.16.4.3 Manual Override
2.16.4.4 MODE 1, MODE 2, MODE 3, MODE 4
2.17 IEEE 1149.1 and 1149.6 Controller
2.17.1 BYPASS Instruction
2.17.2 SAMPLE/PRELOAD Instruction
2.17.2.1 Boundary Scan Chain Order
2.17.2.2 Boundary Scan Chain Order
2.17.2.3 Boundary Scan Exclusion List
2.17.3 EXTEST Instruction
2.17.4 The CLAMP Instruction
2.17.5 The HIGH-Z Instruction
2.17.6 ID CODE Instruction
2.17.7 EXTEST_PULSE Instruction
2.17.8 EXTEST_TRAIN Instruction
2.17.9 PROG_HYST Instruction
2.17.10 AC-JTAG Fault Detection
2.18 Interrupt
2.19 Configuring the 88E1149 Device
2.19.1 Hardware Configuration
2.19.2 Software Configuration - Management Interface
2.19.2.1 Extended Register Access
2.19.2.2 Preamble Suppression
Section 3. Register Description
Section 4. Electrical Specifications
4.1. Absolute Maximum Ratings
4.2. Recommended Operating Conditions
4.3. Package Thermal Information
4.3.1 Thermal Conditions for 176-pin, TQFP Package
4.3.2 Thermal Conditions for 196-pin, TFBGA Package
4.4. Current Consumption (TBD)
4.4.1 Current Consumption AVDDH
4.4.2 Current Consumption VDDC
4.4.3 Current Consumption AVDDT
4.4.4 Current Consumption DVDD
4.4.5 Current Consumption VDDO
4.4.6 Current Consumption Center_Tap
4.5. DC Operating Conditions
4.5.0.1 Digital Pins (TBD)
4.5.1 Internal Resistor Description
4.5.2 IEEE DC Transceiver Parameters
4.5.3 SGMII Interface
4.5.3.1 Transmitter DC Characteristics
4.5.3.2 Common Mode Voltage (Voffset) Calculations
4.5.3.3 Receiver DC Characteristics
4.6. AC Electrical Specifications
4.6.1 Reset Timing
4.6.2 XTAL1/XTAL2 Timing
4.6.3 LED to CONFIG Timing
4.7. SGMII Interface Timing
4.7.1 SGMII Output AC Characteristics
4.7.2 SGMII Input AC Characteristics
4.8. MDC/MDIO Timing
4.8.1 JTAG Timing
4.9. IEEE AC Transceiver Parameters
4.10. Latency Timing
4.10.1 SGMII to 10/100/1000BASE-T Transmit Latency Timing
4.10.2 10/100/1000BASE-T to SGMII Receive Latency Timing
Section 5. Mechanical Drawings
5.1 88E1149 176-Pin TQFP Package Drawing
5.2 88E1149 196-Pin TFBGA Package Drawing
Section 6. Order Information
6.1 Ordering Part Numbers and Package Markings
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88E1149 Datasheet
Integrated 10/100/1000
Gigabit Ethernet Transceiver
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
Doc. No. MV-S101865-00, Rev. B
February 3, 2005
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Document Status
Advanced
Information
Preliminary
Information
Final
Information
Revision Code: Rev. B
Advance
This document contains design specifications for initial product development. Specifications may change
without notice. Contact Marvell Field Application Engineers for more information.
This document contains preliminary data, and a revision of this document will be published at a later date.
Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
This document contains specifications on a product that is in final release. Specifications may change without
notice. Contact Marvell Field Application Engineers for more information.
Technical Publication: 1.00
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express
written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard
to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the
accuracy or completeness of the information, text, graphics, or other items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these
types of equipment or applications.
Marvell assumes no responsibility, either for use of these products or for any infringements of patents and trademarks, or other rights of third parties resulting from its use. No license is granted
under any patents, patent rights, or trademarks of Marvell.
These products may include one or more optional functions. The user has the choice of implementing any particular optional function. Should the user choose to implement any of these optional
functions, it is possible that the use could be subject to third party intellectual property rights. Marvell recommends that the user investigate whether third party intellectual property rights are
relevant to the intended use of these products and obtain licenses as appropriate under relevant intellectual property rights.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"),
to a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national
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3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR
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the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information.
Copyright © 2005. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, GalNet, Libertas, Link Street, NetGX, PHYAdvantage,
Prestera, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. AnyVoltage, Discovery, DSP Switcher, Feroceon, GalTis, Horizon, RADLAN, Raising The Technology Bar, The
Technology Within, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners.
Doc. No. MV-S101865-00 Rev. B
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Document Classification: Proprietary Information
Copyright © 2005 Marvell
February 3, 2005, Advance
CONFIDENTIAL
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•
•
88E1149
•
•
•
•
10/100/1000BASE-T IEEE 802.3 compliant
Highly integrated 4-port physical interface
Supports Serial Gigabit Media Independent Interface
(SGMII)
Integrated Virtual Cable Tester™ (VCT™) cable diag-
nostic feature
"Downshift" mode for two-pair cable installations
User programmable individual/group MDC/MDIO sup-
port
Innovative power management design to reduce on-
chip power by as much as 50%
Fully integrated digital adaptive equalizers, echo can-
cellers, and crosstalk cancellers
Automatic MDI/MDIX crossover for all 3 speeds of oper-
ation including 100BASE-TX and 10BASE-T
Automatic polarity correction
IEEE 802.3u compliant Auto-Negotiation
Direct drive LED support
Loopback mode for diagnostics
Supports IEEE 1149.1 JTAG and 1149.6 AC JTAG
Low power dissipation Pave = 0.6 watts/port
•
•
•
•
•
•
• Manufactured in 176-Pin TQFP and 196-Pin TFBGA
FEATURES
•
•
•
Integrated 10/100/1000 Gigabit Ethernet Transceiver
OVERVIEW
The AlaskaTM Quad family of single-chip devices
contains four independent Gigabit Ethernet trans-
ceivers on a single monolithic IC. Each transceiver
performs all the physical layer functions for
100BASE-TX and 1000BASE-T full or half-duplex
Ethernet on CAT 5 twisted pair cable, and 10BASE-
T full or half-duplex Ethernet on CAT 3, 4, and 5
cable.
The Alaska 88E1149 device supports the Serial
Gigabit Media Independent Interface (SGMII) for
direct connection to a MAC/Switch port.
The 88E1149 device is fully compliant with the IEEE
802.3 standard. They include the PMD, PMA, and
PCS sublayers. They perform PAM5, 8B/10B,
4B/5B, MLT-3, NRZI, and Manchester encod-
ing/decoding; digital clock/data recovery; stream
cipher scrambling/descrambling; digital adaptive
equalization for the receiver data path as well as
digital filtering for pulse-shaping for the line trans-
mitter; and Auto-Negotiation and management
functions.
The 88E1149 device support Auto-MDI/MDIX at all
three speeds to enable easier installation and
reduced installation costs.
The 88E1149 device uses advanced mixed-signal
processing to perform equalization, echo and
crosstalk cancellation, data recovery, and error cor-
rection at a gigabit per second data rate. The
device achieves robust performance in noisy envi-
ronments with very low power dissipation.
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
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Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S101865-00, Rev. B
February 3, 2005, Advanced
Copyright © 2005 Marvell
packages
Page 3
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88E1149
Integrated 10/100/1000 Gigabit Ethernet Transceiver
M
a
g
n
e
t
i
c
s
Ethernet MAC
SGMII
Ethernet MAC
Ethernet MAC
RJ45
RJ45
RJ45
RJ45
10/100/1000 Mbps
Ethernet MAC
10/100/1000 Mbps
10/100/1000 Mbps
10/100/1000 Mbps
88E1149 Device Application
Transceiver
Media Types:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
AlaskaTM Quad
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Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S101865-00, Rev. B
February 3, 2005, Advanced
Copyright © 2005 Marvell
Page 4
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SECTION 1. SIGNAL DESCRIPTION ...................................................................8
1.1 Pin Description...............................................................................................................8
1.1.1
Pin Type Definitions............................................................................................................ 8
88E1149 176-Pin TQFP Package...................................................................................9
88E1149 196-Pin TFBGA Package..............................................................................10
1.2
1.3
Table of Contents
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SECTION 2. FUNCTIONAL SPECIFICATIONS .....................................................30
2.1 Copper Media Interface ...............................................................................................31
2.2 MAC Interface...............................................................................................................31
2.3 Loopback ......................................................................................................................34
2.3.1 MAC Interface Loopback.................................................................................................. 34
Line Loopback .................................................................................................................. 35
2.3.2
External Loopback............................................................................................................ 36
2.3.3
2.4 Synchronizing FIFO .....................................................................................................37
2.5 Copper Media Transmit and Receive Function .........................................................37
2.5.1
Transmit Side Network Interface ...................................................................................... 37
2.5.2
Encoder ............................................................................................................................ 37
2.5.3 Receive Side Network Interface ....................................................................................... 38
2.5.4 Decoder............................................................................................................................ 39
2.6 Power Supplies ............................................................................................................40
AVDDH............................................................................................................................. 40
2.6.1
VDDC ............................................................................................................................... 40
2.6.2
2.6.3
AVDDT ............................................................................................................................. 40
2.6.4 DVDD ............................................................................................................................... 40
2.6.5
VDDO ............................................................................................................................... 40
Power Supply Sequencing ............................................................................................... 40
2.6.6
2.7 Power Management .....................................................................................................41
Low Power Modes............................................................................................................ 41
Low Power Operating Modes ........................................................................................... 41
SGMII Effect on Low Power Modes.................................................................................. 42
2.8 Auto-Negotiation..........................................................................................................43
10/100/1000BASE-T Auto-Negotiation............................................................................. 43
SGMII Auto-Negotiation.................................................................................................... 44
2.9 Downshift Feature........................................................................................................47
2.10 Virtual Cable Tester™ (VCT™)....................................................................................48
2.11 Data Terminal Equipment (DTE) Detect .....................................................................50
2.12 CRC Error Counter and Frame Counter.....................................................................51
2.12.1 Enabling The CRC Error Counter and Frame Counter..................................................... 51
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S101865-00, Rev. B
February 3, 2005, Advance
Copyright © 2005 Marvell
2.7.1
2.7.2
2.7.3
2.8.1
2.8.2
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88E1149
Integrated 10/100/1000 Gigabit Ethernet Transceiver
2.13 Packet Generator..........................................................................................................51
2.14 MDI/MDIX Crossover ....................................................................................................52
2.15 Polarity Correction .......................................................................................................53
2.16 LED ................................................................................................................................54
2.16.1 LED Polarity...................................................................................................................... 55
2.16.2 Pulse Stretching and Blinking........................................................................................... 56
2.16.3 Bi-Color LED Mixing ......................................................................................................... 57
2.16.4 Modes of Operation .......................................................................................................... 58
2.17 IEEE 1149.1 and 1149.6 Controller..............................................................................63
2.17.1 BYPASS Instruction.......................................................................................................... 63
2.17.2 SAMPLE/PRELOAD Instruction ....................................................................................... 63
2.17.3 EXTEST Instruction .......................................................................................................... 70
2.17.4 The CLAMP Instruction .................................................................................................... 70
2.17.5 The HIGH-Z Instruction .................................................................................................... 70
2.17.6 ID CODE Instruction ......................................................................................................... 70
2.17.7 EXTEST_PULSE Instruction ............................................................................................ 70
2.17.8 EXTEST_TRAIN Instruction ............................................................................................ 71
2.17.9 PROG_HYST Instruction................................................................................................. 71
2.17.10 AC-JTAG Fault Detection ................................................................................................ 72
2.18 Interrupt.........................................................................................................................75
2.19 Configuring the 88E1149 Device.................................................................................76
2.19.1 Hardware Configuration................................................................................................... 76
2.19.2 Software Configuration - Management Interface.............................................................. 78
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SECTION 3. REGISTER DESCRIPTION............................................................. 80
4.3.1
4.3.2
SECTION 4. ELECTRICAL SPECIFICATIONS................................................... 118
4.1. Absolute Maximum Ratings ......................................................................................118
4.2. Recommended Operating Conditions......................................................................119
4.3. Package Thermal Information ...................................................................................120
Thermal Conditions for 176-pin, TQFP Package............................................................ 120
Thermal Conditions for 196-pin, TFBGA Package ......................................................... 121
4.4. Current Consumption (TBD)......................................................................................122
4.4.1 Current Consumption AVDDH........................................................................................ 122
4.4.2 Current Consumption VDDC .......................................................................................... 122
4.4.3 Current Consumption AVDDT ........................................................................................ 122
4.4.4 Current Consumption DVDD .......................................................................................... 122
4.4.5 Current Consumption VDDO .......................................................................................... 123
4.4.6 Current Consumption Center_Tap ................................................................................. 123
CONFIDENTIAL
Doc. No. MV-S101865-00,Rev. B
Document Classification: Proprietary Information
February 3, 2005, Advance
Copyright © 2005 Marvell
Page 6
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4.7.1
4.7.2
4.5.1
4.5.2
4.5.3
SECTION 5. MECHANICAL DRAWINGS...........................................................140
88E1149 176-Pin TQFP Package Drawing................................................................140
5.1
5.2
88E1149 196-Pin TFBGA Package Drawing.............................................................142
4.5. DC Operating Conditions ..........................................................................................124
Internal Resistor Description .......................................................................................... 124
IEEE DC Transceiver Parameters.................................................................................. 125
SGMII Interface .............................................................................................................. 126
4.6. AC Electrical Specifications......................................................................................131
4.6.1 Reset Timing .................................................................................................................. 131
XTAL1/XTAL2 Timing..................................................................................................... 132
4.6.2
LED to CONFIG Timing.................................................................................................. 133
4.6.3
4.7. SGMII Interface Timing ..............................................................................................134
SGMII Output AC Characteristics................................................................................... 134
SGMII Input AC Characteristics...................................................................................... 134
4.8. MDC/MDIO Timing......................................................................................................135
4.8.1
JTAG Timing................................................................................................................... 136
4.9.
IEEE AC Transceiver Parameters.............................................................................137
4.10. Latency Timing...........................................................................................................138
4.10.1 SGMII to 10/100/1000BASE-T Transmit Latency Timing .............................................. 138
4.10.2 10/100/1000BASE-T to SGMII Receive Latency Timing ............................................... 139
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SECTION 6. ORDER INFORMATION................................................................144
6.1 Ordering Part Numbers and Package Markings......................................................144
Document Classification: Proprietary Information
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Doc. No. MV-S101865-00, Rev. B
February 3, 2005, Advance
Copyright © 2005 Marvell
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88E1149
Integrated 10/100/1000 Gigabit Ethernet Transceiver
1.1 Pin Description
The 88E1149 device is a 10/100/1000BASE-T Gigabit Ethernet transceiver.
Section 1. Signal Description
Definition
Input with hysteresis
Input and output
Input only
Output only
Internal pull-up
Internal pull-down
Open drain output
Tri-state output
DC sink capability
1.1.1 Pin Type Definitions
Pin Type
H
I/O
I
O
PU
PD
D
Z
mA
1k32uww5g31if-ee5107b1 * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1k32uww5g31if-ee5107b1 * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S101865-00, Rev. B
February 3, 2005, Advance
Copyright © 2005 Marvell
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