L06B_256Gb_512Gb_1Tb_datasheet.pdf

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NAND Flash Memory

Features

Part Numbering Information

General Description

Asynchronous, NV-DDR, NV-DDR2 Signal Descriptions

Signal Assignments

Package Dimensions

Architecture

Device and Array Organization

Bus Operation – Asynchronous Interface

Asynchronous Enable/Standby

Asynchronous Bus Idle

Asynchronous Pausing Data Input/Output

Asynchronous Commands

Asynchronous Addresses

Asynchronous Data Input

Asynchronous Data Output

Write Protect

Ready/Busy#

Bus Operation – NV-DDR Interface

NV-DDR Enable/Standby

NV-DDR Bus Idle/Driving

NV-DDR Pausing Data Input/Output

NV-DDR Commands

NV-DDR Addresses

NV-DDR DDR Data Input

NV-DDR Data Output

Write Protect

Ready/Busy#

Bus Operation – NV-DDR2 Interface

Differential Signaling

Warmup Cycles

On-die Termination (ODT)

Self-termination On-die Termination (ODT)

Matrix Termination

Matrix Termination Examples

NV-DDR2 Standby

NV-DDR2 Idle

NV-DDR2 Pausing Data Input/Output

NV-DDR2 Commands

NV-DDR2 Addresses

NV-DDR2 Data Input

NV-DDR2 Data Output

Write Protect

Ready/Busy#

Device Initialization

VPP Initialization

Electronic Mirroring

Activating Interfaces

Activating the Asynchronous Interface

Activating the NV-DDR Interface

Activating the NV-DDR2 Interface

CE# Pin Reduction and Volume Addressing

Initialization Sequence

Volume Appointment Without CE# Pin Reduction

Appointing Volume Addresses

Selecting a Volume

Multiple Volume Operation Restrictions

Volume Reversion

Command Definitions

Reset Operations

RESET (FFh)

SYNCHRONOUS RESET (FCh)

RESET LUN (FAh)

HARD RESET (FDh)

Identification Operations

READ ID (90h)

READ ID Parameter Tables

READ PARAMETER PAGE (ECh)

Parameter Page Data Structure Tables

READ UNIQUE ID (EDh)

Configuration Operations

SET FEATURES (EFh)

GET FEATURES (EEh)

GET/SET FEATURES by LUN (D4h/D5h)

VOLUME SELECT (E1h)

ODT CONFIGURE (E2h)

ZQ Calibration

ZQ Calibration Long (F9h)

ZQ Calibration Short (D9h)

ZQ external resistor value, tolerance, and capacitive loading

Status Operations

READ STATUS (70h)

READ STATUS ENHANCED (78h)

FIXED ADDRESS READ STATUS ENHANCED (71h)

Column Address Operations

CHANGE READ COLUMN (05h-E0h)

CHANGE READ COLUMN ENHANCED (06h-E0h)

CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation

CHANGE WRITE COLUMN (85h)

CHANGE ROW ADDRESS (85h)

Read Operations

READ MODE (00h)

READ PAGE (00h-30h)

READ PAGE CACHE SEQUENTIAL (31h)

READ PAGE CACHE RANDOM (00h-31h)

READ PAGE CACHE LAST (3Fh)

READ PAGE MULTI-PLANE (00h-32h)

Read Retry Operations

Program Operations

PROGRAM PAGE (80h-10h)

PROGRAM PAGE CACHE (80h-15h)

PROGRAM PAGE MULTI-PLANE (80h-11h)

PROGRAM SUSPEND (84h) and PROGRAM RESUME (13h)

Erase Operations

ERASE BLOCK (60h-D0h)

ERASE BLOCK MULTI-PLANE (60h-D1h)

ERASE BLOCK MULTI-PLANE (60h-60h-D0h)

ERASE SUSPEND (61h) and ERASE RESUME (D2h)

Copyback Operations

COPYBACK READ (00h-35h)

COPYBACK PROGRAM (85h–10h)

COPYBACK READ MULTI-PLANE (00h-32h)

COPYBACK PROGRAM MULTI-PLANE (85h-11h)

One-Time Programmable (OTP) Operations

PROGRAM OTP PAGE (80h-10h)

PROTECT OTP AREA (80h-10h)

READ OTP PAGE (00h-30h)

Multi-Plane Operations

Multi-Plane Addressing

Interleaved Die (Multi-LUN) Operations

Error Management

Shared Pages

Output Drive Impedance

AC Overshoot/Undershoot Specifications

Input Slew Rate

Output Slew Rate

Power Cycle and Ramp Requirements

Electrical Specifications

Legacy Package Requirements

Package Electrical Specification and Pad Capacitance

Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous)

Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2)

Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ)

Single-Ended Requirements for Differential signals

Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous)

Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR, NV-DDR2)

Electrical Specifications – Array Characteristics

Asynchronous Interface Timing Diagrams

NV-DDR Interface Timing Diagrams

NV-DDR2 Interface Timing Diagrams

Revision History

Rev. E – 8/15

Rev. D – 7/15

Rev. C – 5/15

Rev. B – 2/15

Rev. A – 12/14

Micron Confidential and Proprietary Advance‡ MLC 256Gb to 4Tb Async/Sync NAND Features NAND Flash Memory MT29F256G08CBCBB, MT29F512G08CECBB, MT29F512G08CFCBB, MT29F1T08CMCBB, MT29F2T08CUCBB, MT29F4T08CTCBB Features • Open NAND Flash Interface (ONFI) 4.0-compliant1 • JEDEC NAND Flash Interoperability (JESD230B) compliant2 • Multiple-level cell (MLC) • Organization – Page size x8: 18,592 bytes (16,384 + 2208 bytes) – Block size: 1024 pages, (16,384K + 2208K bytes) – Plane size: 4 planes x 548 blocks per plane – Device size: 256Gb: 2192 blocks; 512Gb: 4384 blocks; 1Tb: 8768 blocks; 2Tb: 17,536 blocks; 4Tb: 35,072 blocks • NV-DDR2 I/O performance4 – Up to NV-DDR2 timing mode 8 – Clock rate: 3.75ns (NV-DDR2) – Read/write throughput per pin: 533 MT/s • NV-DDR I/O performance 4 – Up to NV-DDR timing mode 5 – Clock rate: 10ns (NV-DDR) – Read/write throughput per pin: 200 MT/s • Asynchronous I/O performance 4 – Up to asynchronous timing mode 5 – tRC/tWC: 20ns (MIN) – Read/write throughput per pin: 50 MT/s • Array performance – Single-Plane EXPRESS READ operation time without/with VPP 64/61µs (TYP) 3 – Single-Plane READ PAGE operation time with- out/with VPP 66/63µs (TYP) 3 – Multi-Plane READ PAGE operation time without/ with VPP 77/63µs (TYP) 3 – Program page without/with VPP: 1300µs/1225µs (TYP) – Erase block: 15ms (TYP) • Operating Voltage Range – VCC: 2.7–3.6V – VCCQ: 1.7–1.95V • Command set: ONFI NAND Flash Protocol • Advanced Command Set – Program cache – Read cache sequential – Read cache random – One-time programmable (OTP) mode – Multi-plane commands – Multi-LUN operations – Read Unique ID – Copyback – SLC Mode6 – Read Retry7 – ZQ Calibration • First block (block address 00h) is valid when ship- ped from factory. For minimum required ECC, see Error Management (page 179).7 • RESET (FFh) required as first command after pow- er-on • Operation status byte provides software method for detecting – Operation completion – Pass/fail condition – Write-protect status • Data strobe (DQS) signals provide a hardware meth- od for synchronizing data DQ in the NV-DDR/NV- DDR2 interface • Copyback operations supported within the plane from which data is read • On-die Termination (ODT) 5 • Quality and reliability7 – Testing methodology: JESD47 – Data retention: See qualification report – May vary for targeted application – Endurance: 3000 PROGRAM/ERASE cycles 5 1 / 0 2 / 8 : e s a e l e R • Operating temperature: – Commercial: 0°C to +70°C – Industrial (IT): -40ºC to +85ºC • Package – 48-pin TSOP – 132-ball BGA Notes: 1. The ONFI 4.0 specification is available at www.onfi.org. 2. The JEDEC specification is available at www.jedec.org/standards-documents. 3. Contact factory for technical details regard- ing Randomization. Array read times listed are without internal randomization. 4. TSOP packaged devices only support inter- face speeds up to 200MT/s in the NV-DDR and NV-DDR2 interfaces. PDF: 09005aef8613a983 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. 1

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features 5. ODT functionality is supported only in NV- DDR2. 6. Contact factory for technical details regard- ing SLC mode. 7. Read Retry operations are required to ach- ieve specified endurance and for general ar- ray data integrity. 5 1 / 0 2 / 8 : e s a e l e R PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Numbering MT 29F 256G 08 C B C B B ES :B Micron Technology NAND Flash 29F = NAND Flash memory Density 256G = 256Gb 512G = 512Gb 1T = 1Tb 2T = 2Tb 4T = 4Tb Device Width 08 = 8 bits Level C Bit/Cell 2-bit I/O Classification B E F M T U Die # of CE# # of R/B# 1 2 2 4 16 8 1 2 2 4 8 4 Common Common 1 2 Separate - 2 CH 2 4 Separate - 2 CH Separate - 2 CH 4 4 Separate - 2 CH Operating Voltage Range C = VCC : 3.3V (2.7–3.6V), V : 1.8V (1.7–1.95V) CCQ Note: 1. Pb-free package. Design Revision B = Second revision Production Status Blank = Production ES = Engineering sample Reserved for Future Use Blank Operating Temperature Range Blank = Commercial (0°C to +70°C) IT = Industrial (-40°C to +85°C) Speed Grade (NV-DDR2 mode - BGA) -3.75 = 533 MT/s Package Code J4 = 132-ball VBGA 12mm x 18mm x 1.0mm1 M4 = 132-ball TBGA 12mm x 18mm x 1.3mm1 M5 = 132-ball LBGA 12mm x 18mm x 1.5mm1 1 WP = 48-pin TSOP 12mm x 20mm x 1.2mm Interface B = Async/NV-DDR/NV-DDR2 only Generation Feature Set B = 2nd set of device features 5 1 / 0 2 / 8 : e s a e l e R PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features Contents General Description ....................................................................................................................................... 14 Asynchronous, NV-DDR, NV-DDR2 Signal Descriptions ................................................................................... 14 Signal Assignments ......................................................................................................................................... 16 Package Dimensions ....................................................................................................................................... 18 Architecture ................................................................................................................................................... 22 Device and Array Organization ........................................................................................................................ 23 Bus Operation – Asynchronous Interface ......................................................................................................... 29 Asynchronous Enable/Standby ................................................................................................................... 29 Asynchronous Bus Idle ............................................................................................................................... 29 Asynchronous Pausing Data Input/Output .................................................................................................. 30 Asynchronous Commands .......................................................................................................................... 30 Asynchronous Addresses ............................................................................................................................ 31 Asynchronous Data Input ........................................................................................................................... 32 Asynchronous Data Output ......................................................................................................................... 33 Write Protect .............................................................................................................................................. 34 Ready/Busy# .............................................................................................................................................. 34 Bus Operation – NV-DDR Interface ................................................................................................................. 37 NV-DDR Enable/Standby ............................................................................................................................ 38 NV-DDR Bus Idle/Driving ........................................................................................................................... 38 NV-DDR Pausing Data Input/Output .......................................................................................................... 39 NV-DDR Commands .................................................................................................................................. 39 NV-DDR Addresses ..................................................................................................................................... 40 NV-DDR DDR Data Input ........................................................................................................................... 41 NV-DDR Data Output ................................................................................................................................. 42 Write Protect .............................................................................................................................................. 44 Ready/Busy# .............................................................................................................................................. 44 Bus Operation – NV-DDR2 Interface ................................................................................................................ 45 Differential Signaling .................................................................................................................................. 46 Warmup Cycles .......................................................................................................................................... 46 On-die Termination (ODT) ......................................................................................................................... 47 Self-termination On-die Termination (ODT) ................................................................................................ 49 Matrix Termination .................................................................................................................................... 50 Matrix Termination Examples ..................................................................................................................... 52 NV-DDR2 Standby ...................................................................................................................................... 56 NV-DDR2 Idle ............................................................................................................................................ 57 NV-DDR2 Pausing Data Input/Output ......................................................................................................... 57 NV-DDR2 Commands ................................................................................................................................. 57 NV-DDR2 Addresses ................................................................................................................................... 58 NV-DDR2 Data Input .................................................................................................................................. 59 NV-DDR2 Data Output ............................................................................................................................... 60 Write Protect .............................................................................................................................................. 61 Ready/Busy# .............................................................................................................................................. 61 Device Initialization ....................................................................................................................................... 62 VPP Initialization ......................................................................................................................................... 64 Electronic Mirroring ....................................................................................................................................... 65 Activating Interfaces ....................................................................................................................................... 68 Activating the Asynchronous Interface ........................................................................................................ 68 Activating the NV-DDR Interface ................................................................................................................. 68 Activating the NV-DDR2 Interface ............................................................................................................... 68 CE# Pin Reduction and Volume Addressing ..................................................................................................... 70 PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 5 1 / 0 2 / 8 : e s a e l e R

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features Initialization Sequence ............................................................................................................................... 72 Volume Appointment Without CE# Pin Reduction ....................................................................................... 73 Appointing Volume Addresses ..................................................................................................................... 74 Selecting a Volume ..................................................................................................................................... 74 Multiple Volume Operation Restrictions ...................................................................................................... 74 Volume Reversion ....................................................................................................................................... 75 Command Definitions .................................................................................................................................... 77 Reset Operations ............................................................................................................................................ 80 RESET (FFh) ............................................................................................................................................... 80 SYNCHRONOUS RESET (FCh) .................................................................................................................... 81 RESET LUN (FAh) ....................................................................................................................................... 82 HARD RESET (FDh) .................................................................................................................................... 83 Identification Operations ................................................................................................................................ 84 READ ID (90h) ............................................................................................................................................ 84 READ ID Parameter Tables .......................................................................................................................... 86 READ PARAMETER PAGE (ECh) .................................................................................................................. 87 Parameter Page Data Structure Tables ..................................................................................................... 89 READ UNIQUE ID (EDh) ........................................................................................................................... 104 Configuration Operations .............................................................................................................................. 105 SET FEATURES (EFh) ................................................................................................................................. 106 GET FEATURES (EEh) ................................................................................................................................ 106 GET/SET FEATURES by LUN (D4h/D5h) .................................................................................................... 107 VOLUME SELECT (E1h) ............................................................................................................................. 120 ODT CONFIGURE (E2h) ............................................................................................................................ 122 ZQ Calibration ........................................................................................................................................... 125 ZQ Calibration Long (F9h) ..................................................................................................................... 126 ZQ Calibration Short (D9h) .................................................................................................................... 127 ZQ external resistor value, tolerance, and capacitive loading ................................................................... 128 Status Operations .......................................................................................................................................... 130 READ STATUS (70h) .................................................................................................................................. 131 READ STATUS ENHANCED (78h) ............................................................................................................... 132 FIXED ADDRESS READ STATUS ENHANCED (71h) .................................................................................... 133 Column Address Operations .......................................................................................................................... 135 CHANGE READ COLUMN (05h-E0h) ......................................................................................................... 135 CHANGE READ COLUMN ENHANCED (06h-E0h) ...................................................................................... 136 CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation ............................................................... 137 CHANGE WRITE COLUMN (85h) ............................................................................................................... 138 CHANGE ROW ADDRESS (85h) .................................................................................................................. 139 Read Operations ............................................................................................................................................ 141 READ MODE (00h) .................................................................................................................................... 143 READ PAGE (00h-30h) ............................................................................................................................... 144 READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 145 READ PAGE CACHE RANDOM (00h-31h) ................................................................................................... 146 READ PAGE CACHE LAST (3Fh) ................................................................................................................. 148 READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 149 Read Retry Operations ............................................................................................................................... 151 Program Operations ...................................................................................................................................... 153 PROGRAM PAGE (80h-10h) ........................................................................................................................ 153 PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 155 PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 157 PROGRAM SUSPEND (84h) and PROGRAM RESUME (13h) ......................................................................... 160 Erase Operations ........................................................................................................................................... 163 PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 5 1 / 0 2 / 8 : e s a e l e R

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features ERASE BLOCK (60h-D0h) ........................................................................................................................... 163 ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 164 ERASE BLOCK MULTI-PLANE (60h-60h-D0h) ............................................................................................ 164 ERASE SUSPEND (61h) and ERASE RESUME (D2h) .................................................................................... 164 Copyback Operations .................................................................................................................................... 168 COPYBACK READ (00h-35h) ...................................................................................................................... 169 COPYBACK PROGRAM (85h–10h) .............................................................................................................. 170 COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 170 COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 171 One-Time Programmable (OTP) Operations ................................................................................................... 172 PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 173 PROTECT OTP AREA (80h-10h) .................................................................................................................. 174 READ OTP PAGE (00h-30h) ........................................................................................................................ 175 Multi-Plane Operations ................................................................................................................................. 176 Multi-Plane Addressing ............................................................................................................................. 176 Interleaved Die (Multi-LUN) Operations ......................................................................................................... 177 Error Management ........................................................................................................................................ 179 Shared Pages ................................................................................................................................................. 180 Output Drive Impedance ............................................................................................................................... 184 AC Overshoot/Undershoot Specifications ....................................................................................................... 188 Input Slew Rate ............................................................................................................................................. 190 Output Slew Rate ........................................................................................................................................... 197 Power Cycle and Ramp Requirements ............................................................................................................ 199 Electrical Specifications ................................................................................................................................. 200 Legacy Package Requirements ................................................................................................................... 200 Package Electrical Specification and Pad Capacitance ................................................................................. 201 Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 203 Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2) ......................... 204 Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 206 Single-Ended Requirements for Differential signals ..................................................................................... 208 Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 209 Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR, NV-DDR2) ......................... 212 Electrical Specifications – Array Characteristics .............................................................................................. 231 Asynchronous Interface Timing Diagrams ...................................................................................................... 233 NV-DDR Interface Timing Diagrams .............................................................................................................. 244 NV-DDR2 Interface Timing Diagrams ............................................................................................................. 266 Revision History ............................................................................................................................................ 289 Rev. E – 8/15 .............................................................................................................................................. 289 Rev. D – 7/15 ............................................................................................................................................. 290 Rev. C – 5/15 .............................................................................................................................................. 292 Rev. B – 2/15 .............................................................................................................................................. 293 Rev. A – 12/14 ............................................................................................................................................ 293 5 1 / 0 2 / 8 : e s a e l e R PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features List of Tables Table 1: Asynchronous, NV-DDR, and NV-DDR2 Signal Definitions ................................................................. 14 Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 28 Table 3: Asynchronous Interface Mode Selection ............................................................................................ 29 Table 4: NV-DDR Interface Mode Selection .................................................................................................... 37 Table 5: NV-DDR2 Interface Mode Selection ................................................................................................... 45 Table 6: On-die Termination DC Electrical Characteristics without Calibration ................................................ 48 Table 7: On-die Termination DC Electrical Characteristics with Calibration ..................................................... 48 Table 8: LUN state for Matrix Termination ...................................................................................................... 50 Table 9: Volume appointment for Matrix Termination example ....................................................................... 52 Table 10: Non-Target ODT for Data Output, Target ODT for Data Input settings configuration example ............ 53 Table 11: Parallel Non-Target ODT settings configuration example .................................................................. 55 Table 12: Command Set ................................................................................................................................. 77 Table 13: Read ID Parameters for Address 00h ................................................................................................ 86 Table 14: Read ID Parameters for Address 20h ................................................................................................ 86 Table 15: Read ID Parameters for Address 40h ................................................................................................ 86 Table 16: ONFI Parameter Page Data Structure ............................................................................................... 89 Table 17: JEDEC Parameter Page Defintion ..................................................................................................... 97 Table 18: Feature Address Definitions ............................................................................................................ 105 Table 19: GET/SET FEATURES by LUN Operation LUN address cycle decoding .............................................. 107 Table 20: Feature Address 01h: Timing mode ................................................................................................. 108 Table 21: Feature Address 02h: NV-DDR2 configuration ................................................................................. 109 Table 22: Feature Address 30h: VPP ................................................................................................................ 111 Table 23: Feature Address 58h: Volume configuration .................................................................................... 112 Table 24: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 112 Table 25: Feature Address 81h: Programmable R/B# Pull-Down Strength ........................................................ 113 Table 26: Feature Addresses 89h: Read Retry .................................................................................................. 113 Table 27: Feature Address 90h: Array Operation Mode .................................................................................... 114 Table 28: Feature Address DFh: Flag Check Functionality ............................................................................... 114 Table 29: Feature Address F5h: Partial Page Read / Express Read .................................................................... 115 Table 30: Feature Address F6h: Sleep Lite ...................................................................................................... 117 Table 31: LUN state for Matrix Termination with Sleep Lite Feature ................................................................ 119 Table 32: Volume Address ............................................................................................................................. 121 Table 33: ODT Configuration Matrix ............................................................................................................. 122 Table 34: LUN address cycle decoding ........................................................................................................... 128 Table 35: I/O Drive Strength Settings ............................................................................................................. 128 Table 36: Status Register Definition ............................................................................................................... 130 Table 37: R1 address cycle decoding for FIXED ADDRESS READ STATUS ENHANCED (71h) Operation ............ 134 Table 38: PROGRAM SUSPEND (84h) Status Details ....................................................................................... 160 Table 39: ERASE SUSPEND (61h) Status Details ............................................................................................. 165 Table 40: ERASE SUSPEND (61h) behavior for ERASE operations ................................................................... 166 Table 41: OTP Area Details ............................................................................................................................ 173 Table 42: Error Management Details ............................................................................................................. 179 Table 43: Shared Pages ................................................................................................................................. 180 Table 44: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) ...................................................................... 184 Table 45: Output Drive Strength Impedance Values without ZQ Calibration (VCCQ = 1.7–1.95V) ....................... 184 Table 46: Output Drive Strength Impedance Values with ZQ Calibration (VCCQ = 1.7–1.95V) ............................ 185 Table 47: Output Drive Sensitivity with ZQ Calibration ................................................................................... 186 Table 48: Output Driver Voltage and Temperature Sensitivity with ZQ Calibration ........................................... 186 Table 49: Pull-Up and Pull-Down Output Impedance Mismatch without ZQ Calibration for Asynchronous, NV- DDR and NV-DDR2 ................................................................................................................................... 186 PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 5 1 / 0 2 / 8 : e s a e l e R

Micron Confidential and Proprietary Advance MLC 256Gb to 4Tb Async/Sync NAND Features Table 50: Pull-Up and Pull-Down Output Impedance Mismatch with ZQ Calibration for NV-DDR2 .................. 187 Table 51: Aynchronous Overshoot/Undershoot Parameters ........................................................................... 188 Table 52: NV-DDR Overshoot/Undershoot Parameters .................................................................................. 188 Table 53: NV-DDR2 Overshoot/Undershoot Parameters ................................................................................. 188 Table 54: Test Conditions for Input Slew Rate ................................................................................................ 190 Table 55: NV-DDR Maximum and Minimum Input Slew Rate ......................................................................... 190 Table 56: Input Slew Rate derating for NV-DDR (VCCQ = 1.7–1.95V) ................................................................. 190 Table 57: NV-DDR2 Maximum and Minimum Input Slew Rate ....................................................................... 191 Table 58: Input Slew Rate derating for NV-DDR2 single-ended (VCCQ = 1.7–1.95V) .......................................... 192 Table 59: Input Slew Rate derating for NV-DDR2 differential (VCCQ = 1.7–1.95V) ............................................. 192 Table 60: Test Conditions for Output Slew Rate .............................................................................................. 197 Table 61: Output Slew Rate for Single-Ended Asynchronous, NV-DDR, or NV-DDR2 (VCCQ = 1.7–1.95V) without ZQ Calibration ........................................................................................................................................... 197 Table 62: Output Slew Rate for Differential NV-DDR2 (VCCQ = 1.7-1.95) without ZQ Calibration ....................... 197 Table 63: Output Slew Rate for Differential NV-DDR2 (VCCQ = 1.7-1.95) with ZQ Calibration ............................ 198 Table 64: Output Slew Rate Matching Ratio for NV-DDR2 without ZQ Calibration ........................................... 198 Table 65: Output Slew Rate Matching Ratio for NV-DDR2 with ZQ Calibration ................................................ 198 Table 66: Power Cycle Requirements ............................................................................................................. 199 Table 67: Absolute Maximum DC Ratings by Device ....................................................................................... 200 Table 68: Recommended Operating Conditions ............................................................................................. 200 Table 69: Valid Blocks per LUN ...................................................................................................................... 200 Table 70: Capacitance: 48-Pin TSOP Package ................................................................................................. 201 Table 71: Package Electrical Specifications .................................................................................................... 201 Table 72: LUN Pad Specifications .................................................................................................................. 202 Table 73: Test Conditions .............................................................................................................................. 202 Table 74: DC Characteristics and Operating Conditions (Asynchronous Interface) 1.8V VCCQ ........................... 203 Table 75: DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2 Interface) 1.8V VCCQ ................... 204 Table 76: Asynchronous/NV-DDR DC Characteristics and Operating Conditions (1.8V VCCQ) .......................... 206 Table 77: NV-DDR2 DC Characteristics and Operating Conditions for Single-Ended signals (1.8V VCCQ) ........... 206 Table 78: NV-DDR2 DC Characteristics and Operating Conditions for Differential signals (1.8V VCCQ) .............. 207 Table 79: Single-Ended Levels for RE_t, RE_c, DQS_t, DQS_c for NV-DDR2 (1.8V VCCQ) ................................... 208 Table 80: Differential AC Input/Ouput Parameters ......................................................................................... 208 Table 81: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 209 Table 82: AC Characteristics: NV-DDR Command, Address, and Data ............................................................. 212 Table 83: AC Characteristics: NV-DDR2 Command, Address, and Data for modes 0 - 4 .................................... 215 Table 84: AC Characteristics: NV-DDR2Command, Address, and Data for timing modes 5 - 7 .......................... 221 Table 85: AC Characteristics: NV-DDR2 Command, Address, and Data for timing modes 8 - 10 ........................ 225 Table 86: Array Characteristics ...................................................................................................................... 231 5 1 / 0 2 / 8 : e s a e l e R PDF: 09005aef8613a983 L06B_256Gb_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf - Rev. E 8/2015 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

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