Signal Integrity Effects in Custom IC and ASIC Designs

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SIGNAL INTEGRITY EFFECTS IN CUSTOM IC AND ASIC DESIGNS

IEEE Press 445 Hoes Lane, P.O. Box 1331 Piscataway, NJ 08855-1331 Stamatios V. Kartalopoulos, Editor in Chief M.Akay J. B. Anderson R. J. Baker J. E. Brewer M. Eden M. E. El-Hawary R. J. Herrick R. F. Hoyt D. Kirk M. Padgett M. S. Newman W. D. Reeve G. Zobrist Kenneth Moore, Director ofIEEE Press Catherine Faduska, Senior Acquisitions Editor John Griffin, Acquisitions Editor Anthony VenGraitis, Project Editor Technical Reviewers Prashant Saxena, Intel Corporation Laurence H. Cooke, Independent Consultant Fred C. Ford, Cadence Design Systems, Inc. Louis K. Scheffer, Cadence Design Systems, Inc. Cover image provided by: Michael W. Davidson National High Magnetic Field Laboratory Florida State University

SIGNAL INTEGRITY EFFECTS IN CUSTOM IC AND ASIC DESIGNS Edited by Raminderpal Singh Mixed-Signal Design Kits IBM +IEEE IEEE Press roWILEY. ~INTERSCIENCE JOHN WILEY & SONS, INC.

This book is printed on acid-free paper. Copyright ©2002 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978)750-8400, fax (978)750-4744. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY 10158-0012, (212)850-6011, fax (212)850-6008. E-Mail: PERMREQ@WILEY.COM. For ordering and customer service, call 1-800-CALL WILEY. Library of Congress Cataloging-in-Publication is available. ISBN 0-471-15042-8 Printed in the United States of America. 10 9 8 7 6 5 4 3 2

Contents FOREWORD From the Early Days of CMOS to Today L. H. Cooke Signal Integrity: A Problem for Design and CAD Engineers L. Scheffer PREFACE ACKNOWLEDGMENTS Signal Integrity Effects in System-on-Chip Designs-A Designer's Perspective L. Cooke, M. Goossens, P. Hoxey, T. Inoue, D. Overhauser, P. Saxena, and R. Singh (Original Paper) PART 1 INTERCONNECT CROSSTALK Thtorial Harmony: Static Noise Analysis of Deep SubmicronDigital Integrated Circuits K. L. Shepard, V. Narayanan, and R. Rose (IEEE Transactions on Computer-Aided Design ofInteg rated Circuits and Systems, August 1999) FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program K. Nabors and J. White (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 1991) Modeling, Analysis Efficient Coupled Noise Estimation for On-Chip Interconnects A. Devgan (Proceedings ofthe International Conference on Computer-Aided Design, November 1997) Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise P. Chen, D. A. Kirkpatrick, and K. Keutzer (Proceedings ofthe International Conference on Computer Aided Design, November 2000) Digital Sensitivity: Predicting Signal Interaction using Functional Analysis D. A. Kirkpatrick and A. L. Sangiovanni-Vincentelli (Proceedings of the International Conference on Computer-Aided Design, November 1996) Optimization Crosstalk Reduction for VLSI A. Vittal and M. Marek-Sadowska (IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, March 1997) Noise-aware Repeater Insertion and Wire Sizing For On-Chip Interconnect Hierarchical Moment-Matching C. Chen and N. Menezes (Proceedings of the Design Automation Conference, June 1999) Post Global Routing Crosstalk Synthesis T. Xue, E. S. Kuh, and D. Wang (IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, December 1997) xi xiii xv xvi 1 13 15 35 49 55 63 69 79 85

vi CONTENTS Minimum Crosstalk Channel Routing T. Gao and C. L. Liu (IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, May 1996) Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design J.-S. Yim and C.-M. Kyung (Proceedings ofthe Design Automation Conference, June 1999) A Postprocessing Algorithm for Crosstalk-driven Wire Perturbation P. Saxena and C. L. Liu (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2000) Design Noise in Digital Dynamic CMOS Circuits P. Larsson and C. Svensson (IEEE Journal ofSolid-State Circuits, June 1994) Design of Dynamic Circuits with Enhanced Noise Tolerance S. Bobba and I. N. Hajj (Proceedings of the ASIC/SOC Conference, September 1999) Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design K.-W. Kim, K.-H. Baek, N. Shanbhag, C. L. Liu, and S. Kang (Proceedings of the International Conference on Computer-Aided Design, November 2000) RelatedTopic: Issues with EmergingProcessesand CircuitStyles High Frequency Simulation and Characterization of Advanced Copper Interconnects C. Cregut, G. Le Carval, J. Chilo (Proceedings of the International Conference on Interconnect Tech- nology, May 1999) Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-an-Insulator Technology K. L. Shepard and D.-J. Kim (Proceedings of the Design Automation Conference, June 2000) Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation C.-H. Cheng, S.-C. Chang, S.-D. Li, W.-B. Jone, and J.-S. Wang (Proceedings of the International Conference on Computer-Aided Design, November 2000) PART2 INDUCTANCE EFFECTS Thtorial On-Chip Wiring Design Challenges for Gigahertz Operation A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and P. J. Restle (Special Proceedings ofIEEE, June 2001) IC Analyses Including Extracted Inductance Models M. W. Beattie and L. T. Pileggi (Proceedings of the Design Automation Conference, June 1999) Extraction FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program M. Kamon, M. J. Tsuk, and J. K. White (IEEE Transactions on Microwave Theory and Techniques, September 1994) Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction K. L. Shepard, D. Sitaram, and Y. Zheng (Proceedings of the International Conference on Computer- Aided Design, November 2000) 99 109 115 129 137 143 147 151 155 159 161 189 195 205

CONTENTS Modeling, Analysis On-Chip Inductance Modeling and Analysis K. Gala, V.Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw (Proceedings ofthe Design Automation Conference, June 2000) How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K A. Devgan, H. Ji, and W. Dai (Proceedings ofthe International Conference on Computer-Aided Design, November 2000) Figures of Merit to Characterize the Importance of On-Chip Inductance Y. I. Ismail, E. G. Friedman, and J. L. Neves (Proceedings ofthe Design Automation Conference, June 1998) Design,Optimization Layout Techniques for Minimizing On-Chip Interconnect Self Inductance Y. Massoud, S. Majors, T. Bustami, and J. White (Proceedings of the Design Automation Conference, June 1998) A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise G. Zhong, C.-K. Koh, and K. Roy (Proceedings of the International Conference on Computer-Aided Design, November 2000) PART 3 POWER GRID AND DISTRIBUTION NOISE Thtorial Full-Chip Verification of UDSM Designs R. Saleh, D. Overhauser, and S. Taylor (Proceedings ofthe International Conference on Computer-Aided Design, November 1998) Power Supply Noise in Future IC's: A Crystal Ball Reading P. Larsson (Proceedings of the Custom Integrated Circuits Conference, May 1999) Modeling, Analysis A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs J.-S. Yim, S.-O. Bae, and C.-M. Kyung (Proceedings ofthe Design Automation Conference, June 1999) Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design H. H. Chen and D. D. Ling (Proceedings of the Design Automation Conference, June 1997) Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices Y.-M. Jiang, K.-T. Cheng (Proceedings of the Design Automation Conference, June 1999) Full-Chip Signal Interconnect Analysis for Electromigration Reliability S. Rochel and N. S. Nagaraj (Proceedings ofthe First International Symposium on Quality Electronic Design, March 2000) Optimization Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits R. X. Gu and M. I. Elmasry (IEEE Journal ofSolid-State Circuits, May 1996) Simulation and Optimization of the Power Distribution Network in VLSI Circuits G. Bai, S. Bobba, and I. N. Hajj (Proceedings of the International Conference on Computer-Aided Design, November 2000) Design Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed Mode IC's M. Ingels and M. S. Steyaert (IEEE Journal ofSolid-State Circuits, July 1997) vii 213 219 225 231 237 243 245 253 261 267 273 279 283 291 297

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