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RTL8380M_RTL8382M_RTL8382L_Datasheet_Draft_v0.7.pdf
1. General Description
2. Features
3. System Applications
3.1. RTL8380M: Managed 16*1000M UTP+2*1000Base-X Switch
3.2. RTL8382M: Managed 28*1000M Switch via RTL8218B PHY
3.3. RTL8382M: Managed 20*1000M UTP+4*1000M Combo Switch
3.4. RTL8382M/RTL8382L: Managed/Unmanaged 24*1000M UTP+2*1000Base-X Switch
4. Block Diagrams
4.1. RTL8380M Block Diagram
4.2. RTL8382M Block Diagram
4.3. RTL8382L Block Diagram
5. Pin Assignments and Description (RTL8380M)
5.1. Pin Assignments Figure (RTL8380M)
5.2. Package Identification
5.3. Pin Assignments Table Codes (RTL8380M)
5.4. Pin Assignments Table (RTL8380M)
5.5. Pin Descriptions (RTL8380M)
5.5.1. 1000M Ethernet PHY MDI Interface Pins
5.5.2. SGMII Interface Pins
5.5.3. RSGMII Interface Pins
5.5.4. QSGMII Interface Pins
5.5.5. 1000Base-X/100Base-FX Interface Pins
5.5.6. DDR1/2 SDRAM Interface Pins
5.5.7. DDR3 SDRAM Interface Pins
5.5.8. Master Mode-SPI Flash Interface Pins
5.5.9. UART Interface Pins
5.5.10. LED Interface Pins
5.5.11. GPIO Interface Pins
5.5.12. EJTAG Interface Pins
5.5.13. Configuration Strapping Pins
5.5.14. Miscellaneous Interface Pins
5.5.15. Power and GND Pins
6. Pin Assignments and Description (RTL8382M)
6.1. Pin Assignments Figure (RTL8382M)
6.2. Package Identification
6.3. Pin Assignments Table Codes (RTL8382M)
6.4. Pin Assignments Table (RTL8382M)
6.5. Pin Description (RTL8382M)
6.5.1. 1000M Ethernet PHY MDI Interface Pins
6.5.2. SGMII Interface Pins
6.5.3. RSGMII Interface Pins
6.5.4. QSGMII Interface Pins
6.5.5. 1000Base-X/100Base-FX Interface Pins
6.5.6. DDR1/2 SDRAM Interface Pins
6.5.7. DDR3 SDRAM Interface Pins
6.5.8. Master Mode-SPI Flash Interface Pins
6.5.9. UART Interface Pins
6.5.10. LED Interface Pins
6.5.11. GPIO Interface Pins
6.5.12. EJTAG Interface Pins
6.5.13. Configuration Strapping Pins
6.5.14. Miscellaneous Interface Pins
6.5.15. Power and GND Pins
7. Pin Assignments and Description (RTL8382L)
7.1. Pin Assignments Figure (RTL8382L)
7.2. Package Identification
7.3. Pin Assignments Table Codes (RTL8382L)
7.4. Pin Assignments Table (RTL8382L)
7.5. Pin Descriptions (RTL8382L)
7.5.1. 1000M Ethernet PHY MDI Interface Pins
7.5.2. SGMII Interface Pins
7.5.3. QSGMII Interface Pins
7.5.4. 1000Base-X/100Base-FX Interface Pins
7.5.5. Master Mode-SPI Flash Interface Pins
7.5.6. UART Interface Pins
7.5.7. LED Interface Pins
7.5.8. GPIO Interface Pins
7.5.9. Configuration Strapping Pins
7.5.10. Miscellaneous Interface Pins
7.5.11. Power and GND Pins
8. Switch Function Description
8.1. Hardware Reset and Software Reset
8.1.1. Hardware Reset
8.1.2. Software Reset
8.2. Crystal
8.3. IEEE 802.3az Energy Efficient Ethernet (EEE)
8.4. Layer 2 Learning and Forwarding
8.4.1. Forwarding
8.4.2. Learning
8.4.3. DA/SA Block
8.5. Port Isolation
8.6. IEEE 802.3x Flow Control
8.7. Half Duplex Backpressure
8.7.1. Collision-Based Backpressure (Jam Mode)
8.7.2. Carrier-Based Backpressure (I.e., Defer Mode)
8.8. Layer 2 Multicast and IP Multicast
8.9. IEEE 802.1d/1w/1s (STP/RSTP/MSTP)
8.10. IEEE 802.1p and IEEE 802.1Q (VLAN)
8.11. IEEE 802.1X (Network Access Control)
8.12. Reserved Multicast Address Handling
8.13. Layer 2 Traffic Suppression (Storm Control)
8.14. PIE (Packet Inspection Engine)
8.14.1. Ingress ACL
8.15. Input Bandwidth Control and ACL Traffic Meter
8.15.1. Input Bandwidth Control
8.15.2. ACL Traffic Meter
8.16. IEEE 802.3ad Link Aggregation Protocol
8.17. IEEE 802.1ad VLAN Stacking
8.18. Quality of Service (QoS)
8.19. Packet Scheduling (WRR and WFQ)
8.20. Packet Drop Algorithm (TD)
8.21. Egress Packet Remarking
8.22. Ingress and Egress Port Mirror
8.22.1. Remote Mirror (RAPAN)
8.23. Management Information Base (MIB)
8.24. NIC and CPU Tag Forwarding
8.25. Indirect Table Access
8.26. External PHY Register Access
8.27. Switch Interrupt Indication
9. CPU Function Description
9.1. MIPS-4KEc
9.2. SPI Flash
9.3. SDRAM Interface Configuration (RTL8380M/RTL8382M Only)
10. Interface Descriptions
10.1. QSGMII
10.2. RSGMII
10.3. SGMII
10.4. DDR1 SDRAM (RTL8380M/RTL8382M Only)
10.5. DDR2 SDRAM (RTL8380M/RTL8382M Only)
10.6. DDR3 SDRAM (RTL8380M/RTL8382M Only)
10.7. SPI Flash Interface
10.8. UART
10.9. EJTAG
10.10. I2C Master for EEPROM
10.11. I2C Slave Interface
10.12. SPI Slave Interface
10.13. Serial LED
11. Electrical AC/DC Characteristics
11.1. Absolute Maximum Ratings
11.2. Operating Range
11.3. DC Characteristics
11.4. AC Characteristics
11.4.1. QSGMII Differential Transmitter Characteristics
11.4.2. QSGMII Differential Receiver Characteristics
11.4.3. RSGMII Differential Transmitter Characteristics
11.4.4. RSGMII Differential Receiver Characteristics
11.4.5. SGMII Differential Transmitter Characteristics
11.4.6. SGMII Differential Receiver Characteristics
11.4.7. DDR2 Characteristics
11.4.8. DDR3 Characteristics
11.4.9. SPI Interface Characteristics
11.4.10. SMI (MDC/MDIO) Interface Characteristics
12. Package Information
12.1. LQFP216-E-PAD (24*24mm)
13. Ordering Information
RTL8380M-CG
MULTI-LAYER MANAGED 18*10/100/
RTL8382M-CG
MULTI-LAYER MANAGED 28*10/100/
RTL8382L-CG
UN-MANAGED 26*10/100/1000M-PORT SWITCH CONTROLLERS
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.7
20 February. 2013
Track ID:
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8380M/RTL8382M/RTL8382L
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek Ethernet Switch Controllers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Release Date
2012/05/12
2012/08/08
2012/09/18
2012/10/18
2013/01/24
Summary
Initial draft.
Updated.
Revised the pin description error for MEM_TYPE[1:0] on table 14, 30 and 44.
Add 11.4 AC characteristics；
Update RTL8382L pin assignment；
Add uart1 interface description;
Add GPIO[14:11] and GPO10 description;
Modify the ddr2 and spi flash timing Characteristics；
Add ddr3 timing Characteristics；
2013/02/20 Modify the description for CLK_M_EE[1:0];
2013/05/02 Modify the AC Characteristic of QSGMII VTX-DIFFp-p and VRX-DIFFp-p;
Modify the operating range of the DVDDL, AVDDL, SVDDL, AVDDL_PLL,
PLLVDDL and VDDIO.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
ii
Track ID: Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
3.1.
3.2.
3.3.
3.4.
4.1.
4.2.
4.3.
5.1.
5.2.
5.3.
5.4.
5.5.
6.
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
2.
SYSTEM APPLICATIONS...............................................................................................................................................3
3.
RTL8380M: MANAGED 16*1000M UTP+2*1000BASE-X SWITCH............................................................................3
RTL8382M: MANAGED 28*1000M SWITCH VIA RTL8218B PHY .............................................................................4
RTL8382M: MANAGED 20*1000M UTP+4*1000M COMBO SWITCH ........................................................................5
RTL8382M/RTL8382L: MANAGED/UNMANAGED 24*1000M UTP+2*1000BASE-X SWITCH ..................................6
4.
BLOCK DIAGRAMS.........................................................................................................................................................7
RTL8380M BLOCK DIAGRAM.....................................................................................................................................7
RTL8382M BLOCK DIAGRAM.....................................................................................................................................8
RTL8382L BLOCK DIAGRAM ......................................................................................................................................9
5.
PIN ASSIGNMENTS AND DESCRIPTION (RTL8380M)..........................................................................................10
PIN ASSIGNMENTS FIGURE (RTL8380M) ..................................................................................................................10
PACKAGE IDENTIFICATION.........................................................................................................................................11
PIN ASSIGNMENTS TABLE CODES (RTL8380M)........................................................................................................11
PIN ASSIGNMENTS TABLE (RTL8380M)....................................................................................................................11
PIN DESCRIPTIONS (RTL8380M)...............................................................................................................................16
1000M Ethernet PHY MDI Interface Pins............................................................................................................16
5.5.1.
5.5.2.
SGMII Interface Pins............................................................................................................................................17
5.5.3. RSGMII Interface Pins .........................................................................................................................................18
5.5.4. QSGMII Interface Pins.........................................................................................................................................18
5.5.5.
1000Base-X/100Base-FX Interface Pins ..............................................................................................................18
5.5.6. DDR1/2 SDRAM Interface Pins ...........................................................................................................................19
5.5.7. DDR3 SDRAM Interface Pins ..............................................................................................................................19
5.5.8. Master Mode-SPI Flash Interface Pins ................................................................................................................20
5.5.9. UART Interface Pins.............................................................................................................................................20
LED Interface Pins ..........................................................................................................................................21
5.5.10.
GPIO Interface Pins ........................................................................................................................................21
5.5.11.
5.5.12.
EJTAG Interface Pins......................................................................................................................................21
Configuration Strapping Pins..........................................................................................................................22
5.5.13.
Miscellaneous Interface Pins...........................................................................................................................23
5.5.14.
5.5.15.
Power and GND Pins ......................................................................................................................................24
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382M)..........................................................................................25
PIN ASSIGNMENTS FIGURE (RTL8382M) ..................................................................................................................25
PACKAGE IDENTIFICATION.........................................................................................................................................25
PIN ASSIGNMENTS TABLE CODES (RTL8382M)........................................................................................................26
PIN ASSIGNMENTS TABLE (RTL8382M)....................................................................................................................26
PIN DESCRIPTION (RTL8382M).................................................................................................................................30
1000M Ethernet PHY MDI Interface Pins............................................................................................................30
6.5.1.
6.5.2.
SGMII Interface Pins............................................................................................................................................32
6.5.3. RSGMII Interface Pins .........................................................................................................................................32
6.5.4. QSGMII Interface Pins.........................................................................................................................................32
6.5.5.
1000Base-X/100Base-FX Interface Pins ..............................................................................................................33
6.5.6. DDR1/2 SDRAM Interface Pins ...........................................................................................................................33
6.5.7. DDR3 SDRAM Interface Pins ..............................................................................................................................34
6.5.8. Master Mode-SPI Flash Interface Pins ................................................................................................................35
6.5.9. UART Interface Pins.............................................................................................................................................35
6.5.10.
LED Interface Pins ..........................................................................................................................................35
Track ID: Rev. 0.7
6.1.
6.2.
6.3.
6.4.
6.5.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
iii
RTL8380M/RTL8382M/RTL8382L
Datasheet
7.
8.
8.1.
8.5.
8.6.
8.7.
7.1.
7.2.
7.3.
7.4.
7.5.
6.5.11.
GPIO Interface Pins ........................................................................................................................................35
6.5.12.
EJTAG Interface Pins......................................................................................................................................36
6.5.13.
Configuration Strapping Pins..........................................................................................................................36
6.5.14.
Miscellaneous Interface Pins...........................................................................................................................37
6.5.15.
Power and GND Pins ......................................................................................................................................38
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382L)...........................................................................................39
PIN ASSIGNMENTS FIGURE (RTL8382L) ...................................................................................................................39
PACKAGE IDENTIFICATION.........................................................................................................................................40
PIN ASSIGNMENTS TABLE CODES (RTL8382L).........................................................................................................40
PIN ASSIGNMENTS TABLE (RTL8382L).....................................................................................................................40
PIN DESCRIPTIONS (RTL8382L)................................................................................................................................44
7.5.1.
1000M Ethernet PHY MDI Interface Pins............................................................................................................44
7.5.2.
SGMII Interface Pins............................................................................................................................................46
7.5.3. QSGMII Interface Pins.........................................................................................................................................46
7.5.4.
1000Base-X/100Base-FX Interface Pins ..............................................................................................................46
7.5.5. Master Mode-SPI Flash Interface Pins ................................................................................................................47
7.5.6. UART Interface Pins.............................................................................................................................................47
7.5.7. LED Interface Pins...............................................................................................................................................47
7.5.8. GPIO Interface Pins.............................................................................................................................................48
7.5.9. Configuration Strapping Pins...............................................................................................................................48
7.5.10.
Miscellaneous Interface Pins...........................................................................................................................49
7.5.11.
Power and GND Pins ......................................................................................................................................50
SWITCH FUNCTION DESCRIPTION .........................................................................................................................51
HARDWARE RESET AND SOFTWARE RESET................................................................................................................51
8.1.1. Hardware Reset....................................................................................................................................................51
Software Reset ......................................................................................................................................................51
8.1.2.
CRYSTAL....................................................................................................................................................................51
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................51
LAYER 2 LEARNING AND FORWARDING.....................................................................................................................52
8.4.1. Forwarding...........................................................................................................................................................52
8.4.2. Learning ...............................................................................................................................................................52
8.4.3. DA/SA Block.........................................................................................................................................................52
PORT ISOLATION ........................................................................................................................................................53
IEEE 802.3X FLOW CONTROL ...................................................................................................................................54
HALF DUPLEX BACKPRESSURE..................................................................................................................................55
8.7.1. Collision-Based Backpressure (Jam Mode) .........................................................................................................55
8.7.2. Carrier-Based Backpressure (I.e., Defer Mode) ..................................................................................................55
LAYER 2 MULTICAST AND IP MULTICAST .................................................................................................................56
IEEE 802.1D/1W/1S (STP/RSTP/MSTP)...................................................................................................................56
IEEE 802.1P AND IEEE 802.1Q (VLAN) ..................................................................................................................57
IEEE 802.1X (NETWORK ACCESS CONTROL)............................................................................................................58
RESERVED MULTICAST ADDRESS HANDLING ............................................................................................................59
LAYER 2 TRAFFIC SUPPRESSION (STORM CONTROL) .................................................................................................60
PIE (PACKET INSPECTION ENGINE)............................................................................................................................60
Ingress ACL .....................................................................................................................................................60
INPUT BANDWIDTH CONTROL AND ACL TRAFFIC METER.........................................................................................61
Input Bandwidth Control .................................................................................................................................61
ACL Traffic Meter............................................................................................................................................61
IEEE 802.3AD LINK AGGREGATION PROTOCOL ........................................................................................................61
8.16.
8.17.
IEEE 802.1AD VLAN STACKING...............................................................................................................................62
8.18. QUALITY OF SERVICE (QOS)......................................................................................................................................63
PACKET SCHEDULING (WRR AND WFQ)...................................................................................................................64
8.19.
8.20.
PACKET DROP ALGORITHM (TD)...............................................................................................................................65
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.2.
8.3.
8.4.
8.15.
8.14.1.
8.15.1.
8.15.2.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
iv
Track ID: Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
8.21.
8.22.
8.22.1.
9.1.
9.2.
9.3.
EGRESS PACKET REMARKING ....................................................................................................................................65
INGRESS AND EGRESS PORT MIRROR.........................................................................................................................65
Remote Mirror (RAPAN) .................................................................................................................................66
8.23. MANAGEMENT INFORMATION BASE (MIB) ...............................................................................................................67
8.24. NIC AND CPU TAG FORWARDING .............................................................................................................................67
INDIRECT TABLE ACCESS...........................................................................................................................................68
8.25.
EXTERNAL PHY REGISTER ACCESS...........................................................................................................................68
8.26.
8.27.
SWITCH INTERRUPT INDICATION................................................................................................................................68
9. CPU FUNCTION DESCRIPTION .................................................................................................................................68
MIPS-4KEC...............................................................................................................................................................68
SPI FLASH..................................................................................................................................................................69
SDRAM INTERFACE CONFIGURATION (RTL8380M/RTL8382M ONLY)..................................................................69
INTERFACE DESCRIPTIONS......................................................................................................................................70
10.
10.1. QSGMII ....................................................................................................................................................................70
10.2.
RSGMII.....................................................................................................................................................................70
10.3.
SGMII .......................................................................................................................................................................71
10.4. DDR1 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................72
10.5. DDR2 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................73
10.6. DDR3 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................74
10.7.
SPI FLASH INTERFACE ...............................................................................................................................................74
10.8. UART........................................................................................................................................................................75
EJTAG ......................................................................................................................................................................75
10.9.
I2C MASTER FOR EEPROM ......................................................................................................................................76
10.10.
10.11.
I2C SLAVE INTERFACE...............................................................................................................................................76
10.12. SPI SLAVE INTERFACE...............................................................................................................................................77
10.13. SERIAL LED...............................................................................................................................................................78
11. ELECTRICAL AC/DC CHARACTERISTICS.............................................................................................................80
11.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................80
11.2. OPERATING RANGE....................................................................................................................................................80
11.3. DC CHARACTERISTICS...............................................................................................................................................81
11.4. AC CHARACTERISTICS...............................................................................................................................................81
QSGMII Differential Transmitter Characteristics...........................................................................................81
QSGMII Differential Receiver Characteristics................................................................................................82
RSGMII Differential Transmitter Characteristics ...........................................................................................84
RSGMII Differential Receiver Characteristics................................................................................................85
SGMII Differential Transmitter Characteristics..............................................................................................86
SGMII Differential Receiver Characteristics ..................................................................................................87
DDR2 Characteristics .....................................................................................................................................88
DDR3 Characteristics .....................................................................................................................................89
SPI Interface Characteristics...........................................................................................................................90
SMI (MDC/MDIO) Interface Characteristics..................................................................................................91
12. PACKAGE INFORMATION..........................................................................................................................................92
LQFP216-E-PAD (24*24MM)...................................................................................................................................92
13. ORDERING INFORMATION........................................................................................................................................94
11.4.1.
11.4.2.
11.4.3.
11.4.4.
11.4.5.
11.4.6.
11.4.7.
11.4.8.
11.4.9.
11.4.10.
12.1.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
v
Track ID: Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE (RTL8380M)......................................................................................................................11
TABLE 2. 1000M ETHERNET PHY MDI INTERFACE PINS............................................................................................................16
TABLE 3. SGMII INTERFACE PINS...............................................................................................................................................17
TABLE 4. RSGMII INTERFACE PINS ............................................................................................................................................18
TABLE 5. QSGMII INTERFACE PINS ............................................................................................................................................18
TABLE 6. 1000BASE-X/100BASE-FX INTERFACE PINS ...............................................................................................................18
TABLE 7. DDR1/2 SDRAM INTERFACE PINS..............................................................................................................................19
TABLE 8. DDR3 SDRAM INTERFACE PINS.................................................................................................................................19
TABLE 9. MASTER MODE-SPI FLASH INTERFACE PINS ...............................................................................................................20
TABLE 10. UART INTERFACE PINS...............................................................................................................................................20
TABLE 11. LED INTERFACE PINS ..................................................................................................................................................21
TABLE 12. GPIO INTERFACE PINS ................................................................................................................................................21
TABLE 13. EJTAG INTERFACE PINS..............................................................................................................................................21
TABLE 14. CONFIGURATION STRAPPING PINS ...............................................................................................................................22
TABLE 15. MISCELLANEOUS INTERFACE PINS...............................................................................................................................23
TABLE 16. POWER AND GND PINS................................................................................................................................................24
TABLE 17. PIN ASSIGNMENTS TABLE (RTL8382M) .....................................................................................................................26
TABLE 18. 1000M ETHERNET PHY MDI INTERFACE PINS ...........................................................................................................30
TABLE 19. SGMII INTERFACE PINS...............................................................................................................................................32
TABLE 20. RSGMII INTERFACE PINS............................................................................................................................................32
TABLE 21. QSGMII INTERFACE PINS............................................................................................................................................32
TABLE 22. 1000BASE-X/100BASE-FX INTERFACE PINS...............................................................................................................33
TABLE 23. DDR1/2 SDRAM INTERFACE PINS .............................................................................................................................33
TABLE 24. DDR3 SDRAM INTERFACE PINS ................................................................................................................................34
TABLE 25. MASTER MODE-SPI FLASH INTERFACE PINS...............................................................................................................35
TABLE 26. UART INTERFACE PINS...............................................................................................................................................35
TABLE 27. LED INTERFACE PINS ..................................................................................................................................................35
TABLE 28. GPIO INTERFACE PINS ................................................................................................................................................35
TABLE 29. EJTAG INTERFACE PINS..............................................................................................................................................36
TABLE 30. CONFIGURATION STRAPPING PINS ...............................................................................................................................36
TABLE 31. MISCELLANEOUS INTERFACE PINS...............................................................................................................................37
TABLE 32. POWER AND GND PINS................................................................................................................................................38
TABLE 33. PIN ASSIGNMENTS TABLE (RTL8382L) ......................................................................................................................40
TABLE 34. 1000M ETHERNET PHY MDI INTERFACE PINS ...........................................................................................................44
TABLE 35. SGMII INTERFACE PINS...............................................................................................................................................46
TABLE 37. QSGMII INTERFACE PINS............................................................................................................................................46
TABLE 38. 1000BASE-X/100BASE-FX INTERFACE PINS...............................................................................................................46
TABLE 39. MASTER MODE-SPI FLASH INTERFACE PINS...............................................................................................................47
TABLE 40. UART INTERFACE PINS...............................................................................................................................................47
TABLE 41. LED INTERFACE PINS ..................................................................................................................................................47
TABLE 42. GPIO INTERFACE PINS ................................................................................................................................................48
TABLE 43. CONFIGURATION STRAPPING PINS ...............................................................................................................................48
TABLE 44. MISCELLANEOUS INTERFACE PINS...............................................................................................................................49
TABLE 45. POWER AND GND PINS................................................................................................................................................50
TABLE 46. SPANNING TREE AND RAPID SPANNING TREE ACTION ................................................................................................57
TABLE 47. FORWARDING OF HOST N.............................................................................................................................................59
TABLE 48. RESERVED MULTICAST ADDRESS DEFAULT ACTIONS.................................................................................................59
TABLE 49. UART CONTROL INTERFACE PINS...............................................................................................................................75
TABLE 50. EJTAG INTERFACE PINS..............................................................................................................................................75
TABLE 51. SPI SLAVE INTERFACE.................................................................................................................................................77
TABLE 52. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................80
TABLE 53. RECOMMENDED OPERATING RANGE ...........................................................................................................................80
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
vi
Track ID: Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
List of Figures
TABLE 54. DC CHARACTERISTICS (IO_POWER=3.3V) .................................................................................................................81
TABLE 55. QSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS.........................................................................................81
TABLE 56. QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS...............................................................................................82
TABLE 57. RSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS.........................................................................................84
TABLE 58. RSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS...............................................................................................85
TABLE 59. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS............................................................................................86
TABLE 60. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS .................................................................................................87
TABLE 61. DDR2 SDRAM TIMING CHARACTERISTICS ................................................................................................................88
TABLE 62. DDR3 SDRAM TIMING CHARACTERISTICS ................................................................................................................89
TABLE 63. SPI INTERFACE TIMING CHARACTERISTICS .................................................................................................................90
TABLE 64. SMI (MDC/MDIO) TIMING CHARACTERISTICS ..........................................................................................................91
TABLE 65. ORDERING INFORMATION ............................................................................................................................................94
FIGURE 1. MANAGED 16*1000M UTP+2*1000BASE-X SWITCH..................................................................................................3
FIGURE 2. MANAGED/UNMANAGED 28*1000M SWITCH VIA RTL8218B PHY.............................................................................4
FIGURE 3. MANAGED/UNMANAGED 20*1000M UTP+4*1000M COMBO SWITCH........................................................................5
FIGURE 4. MANAGED/UNMANAGED 24*1000M UTP+2*1000BASE-X SWITCH ...........................................................................6
FIGURE 5. RTL8380M BLOCK DIAGRAM......................................................................................................................................7
FIGURE 6. RTL8382M BLOCK DIAGRAM......................................................................................................................................8
FIGURE 7. RTL8382L BLOCK DIAGRAM .......................................................................................................................................9
FIGURE 8. PIN ASSIGNMENTS (RTL8380M)................................................................................................................................10
FIGURE 9. PIN ASSIGNMENTS (RTL8382M)................................................................................................................................25
FIGURE 10. PIN ASSIGNMENTS (RTL8382L).................................................................................................................................39
FIGURE 11. DA/SA BLOCK ...........................................................................................................................................................52
FIGURE 12. PORT ISOLATION EXAMPLE ........................................................................................................................................53
FIGURE 13. TX PAUSE FRAME FORMAT........................................................................................................................................54
FIGURE 14. FLOW CONTROL STATE MACHINE..............................................................................................................................54
FIGURE 15. SIGNAL TIMING FOR COLLISION-BASED BACKPRESSURE...........................................................................................55
FIGURE 16. SPANNING TREE AND RAPID SPANNING TREE PORT STATES ......................................................................................56
FIGURE 17. IEEE 802.1AD FRAME FORMAT..................................................................................................................................62
FIGURE 18. PRIORITY SELECTION TABLE WEIGHT RULES EXAMPLE 1..........................................................................................63
FIGURE 19. PER-PORT QUEUE MANAGEMENT...............................................................................................................................64
FIGURE 20. RSPAN ENCAPSULATION...........................................................................................................................................66
FIGURE 21. RSPAN ILLUSTRATION ..............................................................................................................................................66
FIGURE 22. NIC ARCHITECTURE...................................................................................................................................................67
FIGURE 23. QSGMII INTERCONNECTION ......................................................................................................................................70
FIGURE 24. RSGMII INTERCONNECTION ......................................................................................................................................70
FIGURE 25. SGMII SIGNAL ...........................................................................................................................................................71
FIGURE 26. DDR1 SDRAM CONFIGURATION ..............................................................................................................................72
FIGURE 27. DDR2 SDRAM CONFIGURATION ..............................................................................................................................73
FIGURE 28. DDR3 SDRAM CONFIGURATION ..............................................................................................................................74
FIGURE 29. SPI FLASH CONFIGURATION.......................................................................................................................................74
FIGURE 30. EJTAG USING A 5-PIN JTAG INTERFACE TO ACCESS DATA BLOCK..........................................................................75
FIGURE 31. 8-BIT EEPROM SEQUENTIAL READ ..........................................................................................................................76
FIGURE 32. I2C SLAVE INTERFACE ACCESS DATA SEQUENCE......................................................................................................76
FIGURE 33. SERIAL LED CONNECTION .........................................................................................................................................78
FIGURE 34. QSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM..............................................................................................82
FIGURE 35. QSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM ....................................................................................................83
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
vii
Track ID: Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
FIGURE 36. RSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ..............................................................................................84
FIGURE 37. RSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM.....................................................................................................85
FIGURE 38. SGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM.................................................................................................86
FIGURE 39. SGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .......................................................................................................87
FIGURE 40. DDR2 TIMING CHARACTERISTICS..............................................................................................................................88
FIGURE 41. DDR3 TIMING CHARACTERISTICS..............................................................................................................................89
FIGURE 42. SPI INTERFACE TIMING ..............................................................................................................................................90
FIGURE 43. SMI (MDC/MDIO) TIMING .......................................................................................................................................91
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
viii
Track ID: Rev. 0.7
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