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Digital Logic Design Using Verilog.pdf
Cover
Preface
Acknowledgments
Contents
About the Author
1 Introduction
Abstract
1.1 Evolution of Logic Design
1.2 System and Logic Design Abstractions
1.3 Integrated Circuit Design and Methodologies
1.3.1 RTL Design
1.3.2 Functional Verification
1.3.3 Synthesis
1.3.4 Physical Design
1.4 Verilog HDL
1.5 Verilog Design Description
1.5.1 Structural Design
1.5.2 Behavior Design
1.5.3 Synthesizable RTL Design
1.6 Key Verilog Terminologies
1.6.1 Verilog Arithmetic Operators
1.6.2 Verilog Logical Operators
1.6.3 Verilog Equality and Inequality Operators
1.6.4 Verilog Sign Operators
1.6.5 Verilog Bitwise Operators
1.6.6 Verilog Relational Operators
1.6.7 Verilog Concatenation and Replication Operators
1.6.8 Verilog Reduction Operators
1.6.9 Verilog Shift Operators
1.7 Summary
2 Combinational Logic Design (Part I)
Abstract
2.1 Introduction to Combinational Logic
2.2 Logic Gates and Synthesizable RTL
2.2.1 NOT or Invert Logic
2.2.2 Two-Input OR Logic
2.2.3 Two-Input NOR Logic
2.2.4 Two-Input AND Logic
2.2.5 Two-Input NAND Logic
2.2.6 Two-Input XOR Logic
2.2.7 Two-Input XNOR Logic
2.2.8 Tri-state Logic
2.3 Arithmetic Circuits
2.3.1 Adder
2.3.1.1 Half Adder
2.3.1.2 Full Adder
2.3.2 Subtractor
2.3.2.1 Half Subtractor
2.3.2.2 Full Subtractor
2.3.3 Multi-bit Adders and Subtractors
2.3.3.1 Four-Bit Full Adder
2.3.3.2 Four-Bit Adder and Subtractor
2.3.4 Comparators and Parity Detectors
2.3.4.1 Binary Comparators
2.3.4.2 Parity Detector
2.3.5 Code Converters
2.3.5.1 Binary to Gray Code Converter
2.3.5.2 Gray to Binary Code Converter
2.4 Summary
3 Combinational Logic Design (Part II)
Abstract
3.1 Multiplexers
3.1.1 Multiplexer as Universal Logic
3.1.1.1 2:1 MUX
3.1.1.2 4:1 MUX Using ‘‘if-else’’
3.1.1.3 4:1 MUX Using ‘‘case’’
3.1.1.4 4:1 MUX Using 2:1 MUX
3.2 Decoders
3.2.1 1 Line to 2 Decoder Using ‘‘case’’
3.2.2 1 Line to 2 Decoder with Enable Using ‘‘case’’
3.2.3 2 Line to 4 Decoder with Enable Using ‘‘case’’
3.2.4 2 Line to 4 Decoder with Active Low Enable Using ‘case’
3.2.5 4 Line to 16 Decoder Using 2:4 Decoder
3.3 Encoders
3.3.1 Priority Encoders
3.4 Summary
4 Combinational Design Guidelines
Abstract
4.1 Use of Blocking Assignments and Event Queue
4.2 Incomplete Sensitivity List
4.3 Continuous Versus Procedural Assignments
4.4 Combinational Loops in Design
4.5 Unintentional Latches in the Design
4.6 Use of Blocking Assignments
4.7 Use of If-Else Versus Case Statements
4.8 MUX Nested or Priority Structure
4.9 Decoder 2:4
4.10 Encoder 4:2
4.11 Missing ‘Default’ Clause in Case
4.12 If-Else with Else Missing
4.13 Logical Equality Versus Case Equality
4.13.1 Logical Equality and Logical Inequality Operators
4.13.2 Case Equality and Case Inequality Operators
4.14 Arithmetic Resource Sharing
4.14.1 With Resource Sharing
4.15 Multiple Driver Assignments
4.16 Summary
5 Sequential Logic Design
Abstract
5.1 Sequential Logic
5.1.1 Positive Level Sensitive D-Latch
5.1.2 Negative Level Sensitive D Latch
5.2 Flip-Flop
5.2.1 Positive Edge Triggered D Flip-Flop
5.2.2 Negative Edge Triggered D Flip-Flop
5.3 Synchronous and Asynchronous Reset
5.3.1 D Flip-Flop Asynchronous Reset
5.3.2 D Flip-Flop Synchronous Reset
5.3.3 Flip-Flop with Load Enable Asynchronous Reset
5.3.4 Flip-Flop with Synchronous Load and Synchronous Reset
5.4 Synchronous Counters
5.4.1 Three Bit Up Counter
5.4.2 Three-Bit Down Counter
5.4.3 Three-Bit Up-Down Counter
5.4.4 Gray Counters
5.4.5 Gray and Binary Counter
5.4.6 Ring Counters
5.4.7 Johnson Counters
5.4.8 Parameterized Counter
5.5 Shift Register
5.5.1 Right and Left Shift
5.5.2 Parallel Input and Parallel Output (PIPO) Shift Register
5.6 Timing and Performance Evaluation
5.7 Asynchronous Counter Design
5.7.1 Ripple Counters
5.8 Memory Modules and Design
5.9 Summary
6 Sequential Design Guidelines
Abstract
6.1 Use of Blocking Assignments
6.1.1 Blocking Assignments and Multiple “Always” Blocks
6.1.2 Blocking Assignments in the Same “Always” Block
6.1.3 Example Blocking Assignment
6.2 Nonblocking Assignments
6.2.1 Example Nonblocking Assignment
6.2.2 Ordering of Non-blocking Assignments
6.3 Latch Versus Flip-Flop
6.3.1 D Flip-Flop
6.3.2 Latch
6.4 Use of Synchronous Versus Asynchronous Reset
6.4.1 Asynchronous Reset D Flip-Flop
6.4.2 Synchronous Reset D Flip_Flop
6.5 Use of If-Else Versus Case Statements
6.6 Internally Generated Clocks
6.7 Gated Clocks
6.8 Use of Pipelining in Design
6.8.1 Design Without Pipelining
6.8.2 Design with Pipelining
6.9 Guidelines for Modeling Synchronous Designs
6.10 Multiple Clocks in the Same Module
6.11 Multi Phase Clocks in the Design
6.12 Guidelines for Modeling Asynchronous Designs
6.13 Summary
7 Complex Designs Using Verilog RTL
Abstract
7.1 ALU Design
7.1.1 Logical Unit Design
7.1.1.1 Logic Unit to Infer Parallel Logic
7.1.1.2 Logical Unit with Registered Inputs and Outputs
7.1.2 Arithmetic Unit
7.1.3 Arithmetic and Logical Unit
7.2 Functions and Tasks
7.2.1 Counting 1’s from the Given String
7.2.2 Module to Count 1’s using Functions
7.3 Parity Generators and Detectors
7.3.1 Parity Generator
7.3.2 Add_Sub_Parity Checker
7.4 Barrel Shifters
7.5 Summary
8 Finite State Machines
Abstract
8.1 Moore Versus Mealy Machines
8.1.1 Level to Pulse Converter
8.2 FSM Encoding Styles
8.2.1 Binary Encoding
8.2.1.1 Two-Bit Binary Counter FSM
8.2.2 Gray Encoding
8.2.2.1 Two-Bit Gray Counter FSM
8.3 One-Hot Encoding
8.4 Sequence Detectors Using FSMs
8.4.1 Sequence Detector Using Mealy Machine Two Always Blocks
8.4.2 Sequence Detector Using Mealy Machine for ‘101’ Sequence
8.5 Improving the Design Performance for FSMs
8.6 Summary
9 Simulation Concepts and PLD-Based Designs
Abstract
9.1 Key Simulation Concepts
9.1.1 Simulation for Blocking and Nonblocking Assignments
9.1.2 Blocking Assignments with Inter-assignment Delays
9.1.3 Blocking Assignments with Intra-assignment Delays
9.1.4 Nonblocking Assignments with Inter-assignment Delays
9.1.5 Nonblocking Assignments with Intra-assignment Delays
9.2 Simulation Using Verilog
9.3 Introduction to PLD
9.4 FPGA as Programmable ASIC
9.4.1 SRAM Based FPGA
9.4.2 Flash-Based FPGA
9.4.3 Antifuse FPGAS
9.4.4 FPGA Building Blocks
9.5 FPGA Design Flow
9.5.1 Design Entry
9.5.2 Design Simulation and Synthesis
9.5.3 Design Implementation
9.5.4 Device Programming
9.6 Logic Realization Using FPGA
9.6.1 Configurable Logic Block
9.6.2 Input–Output Block (IOB)
9.6.3 Block RAM
9.6.4 Digital Clock Manager (DCM) Block
9.6.5 Multiplier Block
9.7 Design Guidelines for FPGA-Based Designs
9.7.1 Verilog Coding Guidelines
9.7.1.1 Blocking Versus Nonblocking Assignments: (Please Refer Chaps. 4 and 6)
9.7.1.2 Priority Versus Parallel Logic
9.7.2 FSM Guidelines
9.7.3 Combinational Design and Combinational Loops
9.7.4 Grouping the Terms
9.7.5 Assignments
9.7.6 Simulation and Synthesis Mismatch
9.7.7 Post-synthesis Verification
9.7.8 Guidelines for Area Optimization
9.7.8.1 Resource Sharing
9.7.8.2 Logic Duplication
9.7.9 Guidelines for Clock
9.7.10 Synchronous Versus Asynchronous Designs
9.7.11 Guidelines for Use of Reset
9.7.12 Guidelines for CDC
9.7.13 Guidelines for Low Power Design
9.7.14 Guidelines for Use of Vendor-Specific IP Blocks
9.8 Summary
References
10 ASIC RTL Synthesis
Abstract
10.1 What Is ASIC?
10.1.1 Full-Custom ASIC
10.1.2 Standard Cell ASIC
10.1.3 Gate Array ASIC
10.2 ASIC Design Flow
10.2.1 Design Specification
10.2.2 RTL Design and Verification
10.2.3 ASIC Synthesis
10.2.4 Physical Design and Implementation
10.3 ASIC Synthesis Using Design Compiler
10.4 ASIC Synthesis Guidelines
10.5 Constraining Design Using Synopsys DC
10.5.1 Reading the Design
10.5.2 Checking of the Design
10.5.3 Clock Definitions
10.5.4 Skew Definition
10.5.5 Defining Input and Output Delay
10.5.6 Defining Minimum (Min) and Maximum (Max) Delay
10.5.7 Design Synthesis
10.5.8 Saving the Design
10.6 Synthesis Optimization Techniques
10.6.1 Resource Allocation
10.6.2 Common Factors and Sub-expressions Use for Optimization
10.6.3 Moving the Piece of Code
10.6.4 Constant Folding
10.6.5 Dead Zone Elimination
10.6.6 Use of Parentheses
10.6.7 Partitioning and Structuring the Design
10.7 Summary
Reference
11 Static Timing Analysis
Abstract
11.1 Setup Time
11.2 Hold Time
11.3 Clock to Q Delay
11.3.1 Frequency Calculations
11.4 Skew in Design
11.5 Timing Paths in Design
11.5.1 Input-to-Register Path
11.5.2 Register-to-Output Path
11.5.3 Register-to-Register Path
11.5.4 Input-to-Output Path
11.6 Timing Goals for the Design
11.7 Min-Max Analysis for ASIC Design
11.8 Fixing Design Violations
11.8.1 Changes at the Architecture Level
11.8.2 Changes at Microarchitecture Level
11.8.3 Optimization During Synthesis
11.9 Fixing Setup Violations in the Design
11.9.1 Logic Duplication
11.9.2 Encoding Methods
11.9.3 Late Arrival Signals
11.9.4 Register Balancing
11.10 Hold Violation Fix
11.11 Timing Exceptions in the Design
11.11.1 Asynchronous and False Paths
11.11.2 Multicycle Paths
11.12 Pipelining and Performance Improvement
11.13 Summary
Reference
12 Constraining ASIC Design
Abstract
12.1 Introduction to Design Constraints
12.2 Compilation Strategy
12.2.1 Top-Down Compilation
12.2.2 Bottom-Up Compilation
12.3 Area Minimization Techniques
12.3.1 Avoid Use of Combinational Logic as Individual Block
12.3.2 Avoid Use of Glue Logic Between Two Modules
12.3.3 Use of set_max_area Attribute
12.3.4 Area Report
12.4 Timing Optimization and Performance Improvement
12.4.1 Design Compilation with ‘map_effort high’
12.4.2 Logical Flattening
12.4.3 Use of group_path Command
12.4.4 Submodule Characterizing
12.4.5 Register Balancing
12.4.6 FSM Optimization
12.4.7 Fixing Hold Violations
12.4.8 Report Command
12.4.8.1 report_qor
12.4.8.2 report_constraints
12.4.8.3 report_contraints_all
12.5 Constraint Validation
12.6 Commands for the DRC, Power, and Optimization
12.7 Summary
References
13 Multiple Clock Domain Design
Abstract
13.1 What Is Multiple Clock Domain?
13.2 What Is Clock Domain Crossing (CDC)
13.3 Level Synchronizers
13.4 Pulse Synchronizers
13.5 MUX Synchronizer
13.6 Challenges in the Design of Synchronizers
13.7 Data Path Synchronizers
13.7.1 Handshaking Mechanism
13.7.2 FIFO Synchronizer
13.7.3 Gray Encoding
13.7.3.1 Gray-to-Binary Converter
13.7.3.2 Binary-to-Gray Converter
13.7.3.3 Practical Gray Code Counter
13.8 Design Guidelines for the Multiple Clock Domain Designs
13.9 FIFO Depth Calculations
13.10 Case Study
13.11 Summary
14 Low Power Design
Abstract
14.1 Introduction to Low Power Design
14.2 Power Dissipation in CMOS Inverter
14.3 Switching and Leakage Power Reduction Techniques
14.3.1 Clock Gating and Clock Tree Optimizations
14.3.2 Operand Isolations
14.3.3 Multiple Vth
14.3.4 Multiple Supply Voltages (MSV)
14.3.5 Dynamic Voltage and Frequency Scaling (DVSF)
14.3.6 Power Gating (Power Shut-Off)
14.3.7 Isolation Logic
14.3.8 State Retention
14.4 Low Power Design Techniques at the RTL Level
14.5 Low Power Design Architecture and UPF Case Study
14.5.1 Isolation Cells
14.5.2 Retention Cells
14.5.3 Level Shifters
14.5.4 Power Sequencing and Scheduling
14.5.4.1 Creation of Power Domains
14.5.4.2 Create Supply Port
14.5.4.3 Create Supply Net
14.5.4.4 Create Power Switch
14.5.4.5 Connect Supply Net
14.6 Summary
15 System on Chip (SOC) Design
Abstract
15.1 What is System on Chip (SOC)?
15.2 SOC Architecture
15.3 SOC Design Flow
15.3.1 IP Design and Reuse
15.3.2 SOC Design Considerations
15.3.3 Hardware Software Codesign
15.3.4 Interface Timings
15.3.4.1 Interface Details and Timing Requirements
15.3.4.2 Reset Clock Requirements
15.3.5 EDA Tool and License Requirements
15.3.6 Developing the Required Prototyping Platform
15.3.7 Developing the Test Plan
15.3.8 Developing the Verification Environment
15.3.9 Prototyping Using FPGAs
15.3.10 ASIC Porting
15.4 SOC Design Challenges
15.5 Case Study
15.6 SOC Design Blocks
15.6.1 Microprocessors or Microcontrollers
15.6.2 Counters and Timers
15.6.3 General Purpose IO Block
15.6.4 Universal Asynchronus Receiver and Transmitter (UART)
15.6.5 Bus Arbitration Logic
15.7 Summary
Appendix I: Synthesizable and Non-Synthesizable Verilog Constructs
Appendix I: Synthesizable and Non-Synthesizable Verilog Constructs
Appendix II: Xilinx Spartan Devices
Appendix II: Xilinx Spartan Devices
Appendix III: Design For Testability
Index
Vaibbhav Taraate
Digital Logic
Design Using
Verilog
Coding and RTL Synthesis
Digital Logic Design Using Verilog
Vaibbhav Taraate
Digital Logic Design Using
Verilog
Coding and RTL Synthesis
123
Vaibbhav Taraate
Semiconductor Training @ Rs.1
Pune, Maharashtra
India
ISBN 978-81-322-2789-2
DOI 10.1007/978-81-322-2791-5
ISBN 978-81-322-2791-5
(eBook)
Library of Congress Control Number: 2016936278
© Springer India 2016
This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names,
in this
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the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
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for any errors or omissions that may have been made.
trademarks, service marks, etc.
Printed on acid-free paper
This Springer imprint is published by Springer Nature
The registered company is Springer (India) Pvt. Ltd.
Dedicated To the Supreme Lord
of Intelligence
And
To All Students and Readers!
Preface
Today’s century is era of miniaturization and high-speed chips, and complex ASICs
are designed in lesser time as compared to before. The technology evolution from
1990 has opened up a new paradigm for ASIC designers. Customers are always
expecting the speedy delivery of the ASIC products and it always accumulates the
good amount of pressure to come up with the high-performance design using less
number of resources.
The evolution in the process node technology in the past decade has started the
real evolution in the semiconductor industry! Many new design techniques and
flows got evolved and stabilized in the past decade. Many EDA tool companies
help designers to complete the design in shorter time span.
In today’s industrial scenario, designer doesn’t spend more time to draw the
schematic to design the digital logic circuits. The EDA tools have enabled the best
design practices by using hardware description languages such as VHDL and
Verilog. The synthesis tools are used primarily to convert
the HDL into the
equivalent logic structure or gate level netlist. The latest EDA tool features have
also improved the productivity and efficiency of the design team!
the digital
The book is organized into three sections; the first section consists of Chaps. 1–9
and describes about
logic design and synthesizable Verilog RTL.
Section I is organized in such a way that reader will be able to have better
understanding of basics of digital logic and synthesizable RTL. This section will be
helpful for the reader to understand the Verilog HDL constructs, hardware infer-
ence, simulation concepts and design guidelines for simple to complex designs. For
the better understanding of the reader, few practical scenarios are included in this
section.
Chapter 1 discusses about
the evolution of the logic design,
logic design
abstraction levels, IC design methodologies and flow, Verilog Module declaration,
and different design styles. This chapter discusses about the simulation and syn-
thesis flow for the Verilog RTL. Even this chapter discusses about the key verilog
HDL features.
vii
viii
Preface
Chapters 2 and 3 describe about the combinational logic design and synthesiz-
able RTL. These chapters also focus on the practical issues and scenarios while
designing the combinational logic using Verilog RTL.
Chapter 4 discusses on the key Verilog coding guidelines and the role of Verilog
in writing an efficient RTL for combinational design.
Chapter 5 discusses about the sequential logic design and covers most of the
simple to complex practical design scenarios. This chapter also deals with the
synthesizable sequential design issues, timing diagrams, and simulation of the
design.
Chapter 6 discusses on the key Verilog coding guidelines and the role of Verilog
in writing an efficient RTL for sequential design.
Chapter 7 describes about the efficient RTL coding for a few complex density
designs and also gives information about the synthesizable results and the key
practical scenarios for the design.
Chapter 8 deals with FSM and design of an efficient FSM using the suitable
FSM encoding styles.
Chapter 9 describes the simulation concepts and PLD based design. Even this
chapter describes about the design guidelines while using PLDs.
Section II consists of Chaps. 10–12 and mainly deals with the logic synthesis,
the static timing analysis, and the constraining ASIC designs. This section is
organized in such a way that reader can have better understanding of synthesizable
Verilog RTL and constraining designs for given specifications. This section also
deals with the static timing analysis and practical issues in performance improve-
ment for the design.
Chapter 10 discusses about the logic synthesis, ASIC design flow, design con-
straints, and gate level netlist.
Chapter 11 describes the static timing analysis and the timing reports and
analysis for complex RTL designs. This chapter also deals with the practical few
practical scenarios in the design and performance improvement technique.
Chapter 12 discusses about the different design constraints and how to tweak
architecture, microarchitecture, and RTL to improve the design performance. This
chapter also deals with the DRC, optimization and performance improvement
scenarios for better understanding of the design constraints.
Section III consists of Chaps.13–15 and mainly discusses on the advanced RTL
design concepts such as multiple clock domain designs, need of synchronizers,
clock domain crossing, low power designs, and SOC-based designs and challenges.
Every chapter in this section discusses about the key practical scenarios using the
efficient Verilog RTL.
Chapter 13 describes about the multiple clock domain designs and the syn-
chronizers and their need. This chapter also focuses on synchronous and asyn-
chronous FIFO buffers and RTL design using Verilog and concludes with a case
study.
Chapter 14 discusses on most of the low power design techniques and the goal of
designers to implement the low power designs. This chapter also deals with the low
power design architecture and power sequencing for the low power designs.
Preface
ix
Chapter 15 focuses on the real-life SOC-based designs and the role of Verilog in
implementing the SOC-based designs.
The book consists of many practical examples from simple to complex logic
depth. This will enable the reader to have better understanding about how to code
an efficient RTL using Verilog. The synthesizable designs, and frequent issues in
the RTL design life cycle are organized in each section for the better understanding.
This book is targeted to the engineering students, inexperienced engineers, and
professionals those who want to implement practical, synthesizable, efficient RTL
using Verilog!
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