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MT47H64M16HR.pdf
DDR2 SDRAM
Features
FBGA Part Number System
State Diagram
Functional Description
Industrial Temperature
Automotive Temperature
General Notes
Functional Block Diagrams
Ball Assignments and Descriptions
Packaging
Package Dimensions
FBGA Package Capacitance
Electrical Specifications – Absolute Ratings
Temperature and Thermal Impedance
Electrical Specifications – IDD Parameters
IDD Specifications and Conditions
IDD7 Conditions
AC Timing Operating Specifications
AC and DC Operating Conditions
ODT DC Electrical Characteristics
Input Electrical Characteristics and Operating Conditions
Output Electrical Characteristics and Operating Conditions
Output Driver Characteristics
Power and Ground Clamp Characteristics
AC Overshoot/Undershoot Specification
Input Slew Rate Derating
Commands
Truth Tables
DESELECT
NO OPERATION (NOP)
LOAD MODE (LM)
ACTIVATE
READ
WRITE
PRECHARGE
REFRESH
SELF REFRESH
Mode Register (MR)
Burst Length
Burst Type
Operating Mode
DLL RESET
Write Recovery
Power-Down Mode
CAS Latency (CL)
Extended Mode Register (EMR)
DLL Enable/Disable
Output Drive Strength
DQS# Enable/Disable
RDQS Enable/Disable
Output Enable/Disable
On-Die Termination (ODT)
Off-Chip Driver (OCD) Impedance Calibration
Posted CAS Additive Latency (AL)
Extended Mode Register 2 (EMR2)
Extended Mode Register 3 (EMR3)
Initialization
ACTIVATE
READ
READ with Precharge
READ with Auto Precharge
WRITE
PRECHARGE
REFRESH
SELF REFRESH
Power-Down Mode
Precharge Power-Down Clock Frequency Change
Reset
CKE Low Anytime
ODT Timing
MRS Command to ODT Update Delay
123.pdf
micron.com
1Gb DDR2 SDRAM Component : MT47H64M16HW-3 IT
DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
• DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Selectable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Industrial temperature (IT) option
• RoHS-compliant
• Supports JEDEC clock jitter specification
1Gb: x4, x8, x16 DDR2 SDRAM
Features
Options1
• Configuration
– 256 Meg x 4 (32 Meg x 4 x 8 banks)
– 128 Meg x 8 (16 Meg x 8 x 8 banks)
– 64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA package (Pb-free) – x16
– 84-ball FBGA (8mm x 12.5mm)
Rev. G, H
• FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (8mm x 11.5mm)
Rev. G
• FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (8mm x 10mm) Rev. H
• FBGA package (lead solder) – x16
– 84-ball FBGA (8mm x 12.5mm)
• FBGA package (lead solder) – x4, x8
– 60-ball FBGA (8mm x 11.5mm)
Rev. G, H
Rev. G
• FBGA package (lead solder) – x4, x8
– 60-ball FBGA (8mm x 10mm) Rev. H
• Timing – cycle time
– 1.875ns @ CL = 7 (DDR2-1066)
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 4 (DDR2-667)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
• Self refresh
– Standard
– Low-power
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
– Industrial (–40°C ≤ TC ≤ 95°C;
–40°C ≤ TA ≤ 85°C)
– Automotive (–40°C ≤ TC , TA ≤ 105ºC)
• Revision
Marking
256M4
128M8
64M16
HR
HQ
CF
HW
HV
JN
-187E
-25E
-25
-3E
-3
-37E
None
L
None
IT
AT
:G/:H
Note:
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
CL = 3
CL = 4
CL = 5
CL = 6
Data Rate (MT/s)
-187E
-25E
-25
-3E
-3
-37E
400
400
400
400
400
400
533
533
533
667
533
533
667
800
667
667
667
n/a
800
800
800
n/a
n/a
n/a
CL = 7
1066
n/a
n/a
n/a
n/a
n/a
tRC (ns)
54
55
55
54
55
55
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
256 Meg x 4
128 Meg x 8
64 Meg x 16
32 Meg x 4 x 8 banks
16 Meg x 8 x 8 banks
8 Meg x 16 x 8 banks
8K
A[13:0] (16K)
BA[2:0] (8)
A[11, 9:0] (2K)
8K
A[13:0] (16K)
BA[2:0] (8)
A[9:0] (1K)
8K
A[12:0] (8K)
BA[2:0] (8)
A[9:0] (1K)
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
Figure 1: 1Gb DDR2 Part Numbers
1Gb: x4, x8, x16 DDR2 SDRAM
Features
Example Part Number: MT47H128M8HQ-37E
MT47H
Configuration
Package
Speed
Revision
-
:
{
:G/:H
Revision
L
IT
AT
Low power
Industrial temperature
Automotive temperature
-187E
-25E
-25
-3E
-3
-37E
Speed Grade
tCK = 1.875ns, CL = 7
tCK = 2.5ns, CL = 5
tCK = 2.5ns, CL = 6
tCK = 3ns, CL = 4
tCK = 3ns, CL = 5
tCK = 3.75ns, CL = 4
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
256M4
128M8
64M16
Package
Pb-free
84-ball 8mm x 12.5mm FBGA
60-ball 8mm x 11.5mm FBGA
60-ball 8mm x 10.0mm FBGA
Lead solder
84-ball 8mm x 12.5mm FBGA
60-ball 8mm x 10mm FBGA
60-ball 8mm x 11.5mm FBGA
HR
HQ
CF
HW
JN
HV
Note:
1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Contents
State Diagram .................................................................................................................................................. 9
Functional Description ................................................................................................................................... 10
Industrial Temperature .............................................................................................................................. 10
Automotive Temperature ........................................................................................................................... 11
General Notes ............................................................................................................................................ 11
Functional Block Diagrams ............................................................................................................................. 12
Ball Assignments and Descriptions ................................................................................................................. 15
Packaging ...................................................................................................................................................... 19
Package Dimensions .................................................................................................................................. 19
FBGA Package Capacitance ......................................................................................................................... 22
Electrical Specifications – Absolute Ratings ..................................................................................................... 23
Temperature and Thermal Impedance ........................................................................................................ 23
Electrical Specifications – IDD Parameters ........................................................................................................ 26
IDD Specifications and Conditions ............................................................................................................... 26
IDD7 Conditions .......................................................................................................................................... 27
AC Timing Operating Specifications ................................................................................................................ 31
AC and DC Operating Conditions .................................................................................................................... 41
ODT DC Electrical Characteristics ................................................................................................................... 42
Input Electrical Characteristics and Operating Conditions ............................................................................... 43
Output Electrical Characteristics and Operating Conditions ............................................................................. 46
Output Driver Characteristics ......................................................................................................................... 48
Power and Ground Clamp Characteristics ....................................................................................................... 52
AC Overshoot/Undershoot Specification ......................................................................................................... 53
Input Slew Rate Derating ................................................................................................................................ 55
Commands .................................................................................................................................................... 68
Truth Tables ............................................................................................................................................... 68
DESELECT ................................................................................................................................................. 72
NO OPERATION (NOP) .............................................................................................................................. 73
LOAD MODE (LM) ..................................................................................................................................... 73
ACTIVATE .................................................................................................................................................. 73
READ ......................................................................................................................................................... 73
WRITE ....................................................................................................................................................... 73
PRECHARGE .............................................................................................................................................. 74
REFRESH ................................................................................................................................................... 74
SELF REFRESH ........................................................................................................................................... 74
Mode Register (MR) ........................................................................................................................................ 74
Burst Length .............................................................................................................................................. 75
Burst Type ................................................................................................................................................. 76
Operating Mode ......................................................................................................................................... 76
DLL RESET ................................................................................................................................................. 76
Write Recovery ........................................................................................................................................... 77
Power-Down Mode .................................................................................................................................... 77
CAS Latency (CL) ........................................................................................................................................ 78
Extended Mode Register (EMR) ....................................................................................................................... 79
DLL Enable/Disable ................................................................................................................................... 80
Output Drive Strength ................................................................................................................................ 80
DQS# Enable/Disable ................................................................................................................................. 80
RDQS Enable/Disable ................................................................................................................................. 80
Output Enable/Disable ............................................................................................................................... 80
On-Die Termination (ODT) ........................................................................................................................ 81
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 81
Posted CAS Additive Latency (AL) ............................................................................................................... 81
Extended Mode Register 2 (EMR2) .................................................................................................................. 83
Extended Mode Register 3 (EMR3) .................................................................................................................. 84
Initialization .................................................................................................................................................. 85
ACTIVATE ...................................................................................................................................................... 88
READ ............................................................................................................................................................. 90
READ with Precharge ................................................................................................................................. 94
READ with Auto Precharge .......................................................................................................................... 96
WRITE .......................................................................................................................................................... 101
PRECHARGE ................................................................................................................................................. 111
REFRESH ...................................................................................................................................................... 112
SELF REFRESH .............................................................................................................................................. 113
Power-Down Mode ....................................................................................................................................... 115
Precharge Power-Down Clock Frequency Change .......................................................................................... 122
Reset ............................................................................................................................................................. 123
CKE Low Anytime ...................................................................................................................................... 123
ODT Timing .................................................................................................................................................. 125
MRS Command to ODT Update Delay ........................................................................................................ 127
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17
Table 4: Input Capacitance ............................................................................................................................ 22
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 23
Table 6: Temperature Limits .......................................................................................................................... 24
Table 7: Thermal Impedance ......................................................................................................................... 25
Table 8: General IDD Parameters .................................................................................................................... 26
Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 27
Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E, G, and H) ................................................ 28
Table 11: AC Operating Specifications and Conditions .................................................................................... 31
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 41
Table 13: ODT DC Electrical Characteristics ................................................................................................... 42
Table 14: Input DC Logic Levels ..................................................................................................................... 43
Table 15: Input AC Logic Levels ..................................................................................................................... 43
Table 16: Differential Input Logic Levels ........................................................................................................ 44
Table 17: Differential AC Output Parameters .................................................................................................. 46
Table 18: Output DC Current Drive ................................................................................................................ 46
Table 19: Output Characteristics .................................................................................................................... 47
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 48
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 49
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 50
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 51
Table 24: Input Clamp Characteristics ........................................................................................................... 52
Table 25: Address and Control Balls ............................................................................................................... 53
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 53
Table 27: AC Input Test Conditions ................................................................................................................ 54
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) ................................................... 56
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) .......................................... 57
Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ..................................................... 60
Table 31: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................ 61
Table 32: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb .................................................. 62
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ..................................... 62
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ..................................... 63
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ..................................... 63
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 68
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 69
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 71
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 72
Table 40: Burst Definition .............................................................................................................................. 76
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 96
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 102
Table 43: Truth Table – CKE ......................................................................................................................... 117
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 3
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 19
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ............................................................................... 20
Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 21
Figure 11: Example Temperature Test Point Location ..................................................................................... 24
Figure 12: Single-Ended Input Signal Levels ................................................................................................... 43
Figure 13: Differential Input Signal Levels ...................................................................................................... 44
Figure 14: Differential Output Signal Levels .................................................................................................... 46
Figure 15: Output Slew Rate Load .................................................................................................................. 47
Figure 16: Full Strength Pull-Down Characteristics ......................................................................................... 48
Figure 17: Full Strength Pull-Up Characteristics ............................................................................................. 49
Figure 18: Reduced Strength Pull-Down Characteristics ................................................................................. 50
Figure 19: Reduced Strength Pull-Up Characteristics ...................................................................................... 51
Figure 20: Input Clamp Characteristics .......................................................................................................... 52
Figure 21: Overshoot ..................................................................................................................................... 53
Figure 22: Undershoot .................................................................................................................................. 53
Figure 23: Nominal Slew Rate for tIS .............................................................................................................. 58
Figure 24: Tangent Line for tIS ....................................................................................................................... 58
Figure 25: Nominal Slew Rate for tIH .............................................................................................................. 59
Figure 26: Tangent Line for tIH ...................................................................................................................... 59
Figure 27: Nominal Slew Rate for tDS ............................................................................................................. 64
Figure 28: Tangent Line for tDS ...................................................................................................................... 64
Figure 29: Nominal Slew Rate for tDH ............................................................................................................ 65
Figure 30: Tangent Line for tDH ..................................................................................................................... 65
Figure 31: AC Input Test Signal Waveform Command/Address Balls ............................................................... 66
Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 66
Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 67
Figure 34: AC Input Test Signal Waveform (Differential) ................................................................................. 67
Figure 35: MR Definition ............................................................................................................................... 75
Figure 36: CL ................................................................................................................................................ 78
Figure 37: EMR Definition ............................................................................................................................. 79
Figure 38: READ Latency ............................................................................................................................... 82
Figure 39: WRITE Latency ............................................................................................................................. 82
Figure 40: EMR2 Definition ........................................................................................................................... 83
Figure 41: EMR3 Definition ........................................................................................................................... 84
Figure 42: DDR2 Power-Up and Initialization ................................................................................................. 85
Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 88
Figure 44: Multibank Activate Restriction ....................................................................................................... 89
Figure 45: READ Latency ............................................................................................................................... 91
Figure 46: Consecutive READ Bursts .............................................................................................................. 92
Figure 47: Nonconsecutive READ Bursts ........................................................................................................ 93
Figure 48: READ Interrupted by READ ........................................................................................................... 94
Figure 49: READ-to-WRITE ............................................................................................................................ 94
Figure 50: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 95
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Figure 51: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 95
Figure 52: Bank Read – Without Auto Precharge ............................................................................................. 97
Figure 53: Bank Read – with Auto Precharge ................................................................................................... 98
Figure 54: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window .................................................. 99
Figure 55: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 100
Figure 56: Data Output Timing – tAC and tDQSCK ......................................................................................... 101
Figure 57: Write Burst ................................................................................................................................... 103
Figure 58: Consecutive WRITE-to-WRITE ...................................................................................................... 104
Figure 59: Nonconsecutive WRITE-to-WRITE ................................................................................................ 104
Figure 60: WRITE Interrupted by WRITE ....................................................................................................... 105
Figure 61: WRITE-to-READ ........................................................................................................................... 106
Figure 62: WRITE-to-PRECHARGE ................................................................................................................ 107
Figure 63: Bank Write – Without Auto Precharge ............................................................................................ 108
Figure 64: Bank Write – with Auto Precharge ................................................................................................. 109
Figure 65: WRITE – DM Operation ................................................................................................................ 110
Figure 66: Data Input Timing ........................................................................................................................ 111
Figure 67: Refresh Mode ............................................................................................................................... 112
Figure 68: Self Refresh .................................................................................................................................. 114
Figure 69: Power-Down ................................................................................................................................ 116
Figure 70: READ-to-Power-Down or Self Refresh Entry .................................................................................. 118
Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 118
Figure 72: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 119
Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 119
Figure 74: REFRESH Command-to-Power-Down Entry ................................................................................. 120
Figure 75: ACTIVATE Command-to-Power-Down Entry ................................................................................ 120
Figure 76: PRECHARGE Command-to-Power-Down Entry ............................................................................ 121
Figure 77: LOAD MODE Command-to-Power-Down Entry ............................................................................ 121
Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 122
Figure 79: RESET Function ........................................................................................................................... 124
Figure 80: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 126
Figure 81: Timing for MRS Command to ODT Update Delay .......................................................................... 127
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 127
Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 128
Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 128
Figure 85: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 129
Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 130
Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 131
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
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