NOR_FLASH数据手册.pdf

发布时间：2022-06-21 发布人：admin 分类：说明书资料大小：2.40M 资料格式：pdf 举报版权申诉

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FEATURES

GENERAL DESCRIPTION

PIN CONFIGURATIONS

PIN DESCRIPTION

BLOCK DIAGRAM

BLOCK DIAGRAM DESCRIPTION

BLOCK STRUCTURE

Table 1-1. MX29LV160DT SECTOR ARCHITECTURE

Table 1-2. MX29LV160DB SECTOR ARCHITECTURE

BUS OPERATION

Table 2-1. BUS OPERATION

Table 2-2. BUS OPERATION

FUNCTIONAL OPERATION DESCRIPTION

WRITE COMMANDS/COMMAND SEQUENCES

REQUIREMENTS FOR READING ARRAY DATA

RESET# OPERATION

SECTOR PROTECT OPERATION

CHIP UNPROTECT OPERATION

HARDWARE WRITE PROTECT

ACCELERATED PROGRAMMING OPERATION

TEMPORARY SECTOR UNPROTECT OPERATION

AUTOMATIC SELECT OPERATION

VERIFY SECTOR PROTECT STATUS OPERATION

DATA PROTECTION

LOW VCC WRITE INHIBIT

WRITE PULSE "GLITCH" PROTECTION

LOGICAL INHIBIT

POWER-UP SEQUENCE

POWER-UP WRITE INHIBIT

POWER SUPPLY DECOUPLING

COMMAND OPERATIONS

TABLE 3. MX29LV160D T/B COMMAND DEFINITIONS

AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY

ERASING THE MEMORY ARRAY

SECTOR ERASE

CHIP ERASE

SECTOR ERASE SUSPEND

SECTOR ERASE RESUME

AUTOMATIC SELECT OPERATIONS

AUTOMATIC SELECT COMMAND SEQUENCE

READ MANUFACTURER ID OR DEVICE ID

VERIFY SECTOR GROUP PROTECTION

RESET

COMMON FLASH MEMORY INTERFACE (CFI) MODE

QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE

Table 4-1. CFI mode: Identification Data Values

Table 4-2. CFI Mode: System Interface Data Values

Table 4-3. CFI Mode: Device Geometry Data Values

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM STRESS RATINGS

OPERATING TEMPERATURE AND VOLTAGE

DC CHARACTERISTICS

SWITCHING TEST CIRCUIT

SWITCHING TEST WAVEFORM

AC CHARACTERISTICS

WRITE COMMAND OPERATION

Figure 1. COMMAND WRITE OPERATION

READ/RESET OPERATION

Figure 2. READ TIMING WAVEFORM

Figure 3. RESET# TIMING WAVEFORM

ERASE/PROGRAM OPERATION

Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

Figure 8. ERASE SUSPEND/RESUME FLOWCHART

Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM

Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM

Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM

Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

SECTOR PROTECT/CHIP UNPROTECT

Figure 13. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)

Figure 14. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv

Figure 15. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv

Table 5. TEMPORARY SECTOR UNPROTECT

Figure 16. TEMPORARY SECTOR UNPROTECT WAVEFORM

Figure 17. TEMPORARY SECTOR UNPROTECT FLOWCHART

Figure 18. SILICON ID READ TIMING WAVEFORM

WRITE OPERATION STATUS

Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)

Figure 20. DATA# POLLING ALGORITHM

Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)

Figure 22. TOGGLE BIT ALGORITHM

Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode)

RECOMMENDED OPERATING CONDITIONS

ERASE AND PROGRAMMING PERFORMANCE

DATA RETENTION

LATCH-UP CHARACTERISTICS

ORDERING INFORMATION

PART NAME DESCRIPTION

PACKAGE INFORMATION

REVISION HISTORY

MX29LV160D T/B MX29LV160D T/B DATASHEET P/N:PM1315 REV. 1.2, DEC. 22, 2011 1

MX29LV160D T/B Contents FEATURES .............................................................................................................................................................5 GENERAL DESCRIPTION .....................................................................................................................................6 PIN CONFIGURATIONS .........................................................................................................................................7 PIN DESCRIPTION .................................................................................................................................................9 BLOCK DIAGRAM ................................................................................................................................................10 BLOCK DIAGRAM DESCRIPTION ...................................................................................................................... 11 BLOCK STRUCTURE ...........................................................................................................................................12 Table 1-1. MX29LV160DT SECTOR ARCHITECTURE ..............................................................................12 Table 1-2. MX29LV160DB SECTOR ARCHITECTURE .............................................................................13 BUS OPERATION .................................................................................................................................................14 Table 2-1. BUS OPERATION ......................................................................................................................14 Table 2-2. BUS OPERATION ......................................................................................................................15 FUNCTIONAL OPERATION DESCRIPTION .......................................................................................................16 WRITE COMMANDS/COMMAND SEQUENCES .......................................................................................16 REQUIREMENTS FOR READING ARRAY DATA .......................................................................................16 RESET# OPERATION ................................................................................................................................17 SECTOR PROTECT OPERATION .............................................................................................................17 CHIP UNPROTECT OPERATION ..............................................................................................................17 HARDWARE WRITE PROTECT .................................................................................................................17 ACCELERATED PROGRAMMING OPERATION ......................................................................................17 TEMPORARY SECTOR UNPROTECT OPERATION ................................................................................18 AUTOMATIC SELECT OPERATION ...........................................................................................................18 VERIFY SECTOR PROTECT STATUS OPERATION .................................................................................18 DATA PROTECTION ...................................................................................................................................18 LOW VCC WRITE INHIBIT .........................................................................................................................18 WRITE PULSE "GLITCH" PROTECTION ...................................................................................................18 LOGICAL INHIBIT .......................................................................................................................................19 POWER-UP SEQUENCE ...........................................................................................................................19 POWER-UP WRITE INHIBIT ......................................................................................................................19 POWER SUPPLY DECOUPLING ...............................................................................................................19 COMMAND OPERATIONS ...................................................................................................................................20 TABLE 3. MX29LV160D T/B COMMAND DEFINITIONS ............................................................................20 AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY ......................................................................21 ERASING THE MEMORY ARRAY ..............................................................................................................21 SECTOR ERASE ........................................................................................................................................22 CHIP ERASE ..............................................................................................................................................23 SECTOR ERASE SUSPEND ......................................................................................................................23 SECTOR ERASE RESUME ........................................................................................................................24 AUTOMATIC SELECT OPERATIONS ........................................................................................................24 AUTOMATIC SELECT COMMAND SEQUENCE .......................................................................................24 P/N:PM1315 REV. 1.2, DEC. 22, 2011 2

MX29LV160D T/B READ MANUFACTURER ID OR DEVICE ID .............................................................................................25 VERIFY SECTOR GROUP PROTECTION .................................................................................................25 RESET .......................................................................................................................................................25 COMMON FLASH MEMORY INTERFACE (CFI) MODE .....................................................................................26 QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ...................................................26 Table 4-1. CFI mode: Identification Data Values .........................................................................................26 Table 4-2. CFI Mode: System Interface Data Values ..................................................................................26 Table 4-3. CFI Mode: Device Geometry Data Values ..................................................................................27 Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values ............................................28 ELECTRICAL CHARACTERISTICS ....................................................................................................................29 ABSOLUTE MAXIMUM STRESS RATINGS ...............................................................................................29 OPERATING TEMPERATURE AND VOLTAGE ..........................................................................................29 DC CHARACTERISTICS ............................................................................................................................30 SWITCHING TEST CIRCUIT ......................................................................................................................31 SWITCHING TEST WAVEFORM ...............................................................................................................31 AC CHARACTERISTICS ............................................................................................................................32 WRITE COMMAND OPERATION .........................................................................................................................33 Figure 1. COMMAND WRITE OPERATION ................................................................................................33 READ/RESET OPERATION .................................................................................................................................34 Figure 2. READ TIMING WAVEFORM ........................................................................................................34 Figure 3. RESET# TIMING WAVEFORM ...................................................................................................35 ERASE/PROGRAM OPERATION ........................................................................................................................36 Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM ......................................................................36 Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ............................................................37 Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM ................................................................38 Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART ....................................................39 Figure 8. ERASE SUSPEND/RESUME FLOWCHART ..............................................................................40 Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM ..........................................................................41 Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM .....................................................................41 Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM ...................................................................42 Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ....................................................43 SECTOR PROTECT/CHIP UNPROTECT ............................................................................................................44 Figure 13. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) .............................44 Figure 14. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv ............................................................45 Figure 15. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv .........................................................46 Table 5. TEMPORARY SECTOR UNPROTECT .........................................................................................47 Figure 16. TEMPORARY SECTOR UNPROTECT WAVEFORM ...............................................................47 Figure 17. TEMPORARY SECTOR UNPROTECT FLOWCHART ..............................................................48 Figure 18. SILICON ID READ TIMING WAVEFORM ..................................................................................49 WRITE OPERATION STATUS ..............................................................................................................................50 Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM) .......................50 Figure 20. DATA# POLLING ALGORITHM .................................................................................................51 P/N:PM1315 REV. 1.2, DEC. 22, 2011 3

MX29LV160D T/B Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM) ............................52 Figure 22. TOGGLE BIT ALGORITHM........................................................................................................53 Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) .................................................................................................................................................54 RECOMMENDED OPERATING CONDITIONS ....................................................................................................55 ERASE AND PROGRAMMING PERFORMANCE ...............................................................................................56 DATA RETENTION ...............................................................................................................................................56 LATCH-UP CHARACTERISTICS .........................................................................................................................56 ORDERING INFORMATION .................................................................................................................................57 PART NAME DESCRIPTION ................................................................................................................................58 PACKAGE INFORMATION ...................................................................................................................................59 REVISION HISTORY ............................................................................................................................................65 P/N:PM1315 REV. 1.2, DEC. 22, 2011 4

MX29LV160D T/B 16M-BIT [2M x 8 / 1M x 16] 3V SUPPLY FLASH MEMORY FEATURES GENERAL FEATURES • Byte/Word mode switchable - 2,097,152 x8 / 1,048,576 x16 • Sector Structure - 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, 64K-Byte x 31 - Provides sector protect function to prevent program or erase operation in the protected sector - Provides chip unprotect function to allow code changing - Provides temporary sector unprotect function for code changing in previously protected sector • Power Supply Operation - Vcc 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to 1.5 x Vcc • Low Vcc write inhibit : Vcc ≤ Vlko • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Functional compatible with MX29LV160C device PERFORMANCE • High Performance - Fast access time: 70ns - Word program time: 11us/word (typical) - Fast erase time: 0.7s/sector, 15s/chip (typical) • Low Power Consumption - Low active read current: 5mA (typical) at 5MHz - Low standby current: 5uA (typical) • Typical 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC - Provide accelerated program capability PACKAGE • 48-Pin TSOP • 48-Ball CSP (TFBGA) • 48-Ball WFBGA/XFLGA • All devices are RoHS Compliant P/N:PM1315 REV. 1.2, DEC. 22, 2011 5

MX29LV160D T/B GENERAL DESCRIPTION MX29LV160DT/B is a 16Mbit flash memory that can be organized as 2Mbytes of 8 bits each or as 1Mwords of 16 bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 32 equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or Bottom-Boot device. The outermost one sector at the top or at the bottom are respectively the boot blocks for this device. The MX29LV160DT/B is offered in a 48-pin TSOP, 48-ball XFLGA/WFBGA and a 48-ball CSP(TFBGA) JEDEC standard package. These packages are offered in leaded, as well as lead-free versions that are compliant to the RoHS specifications. The software algorithm used for this device also adheres to the JEDEC standard for single power supply devices. These flash parts can be programmed in system or on commercially available EPROM/ Flash programmers. Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When used with high speed processors, the 70ns read access time of this flash memory permits operation with minimal time lost due to system timing delays. The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write. The user only needs to provide a write command to the command register. The on-chip state machine automati- cally controls the program and erase functions including all necessary internal timings. Since erase and write operations take much longer time than read operations, erase/write can be interrupted to perform read opera- tions in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation. These devices are manufactured at the Macronix fabrication facility using the time tested and proven Macronix's advance technology. This proprietary non-epi process provides a very high degree of latch-up protection for stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC. With low power consumption and enhanced hardware and software features, this flash memory retains data reli- ably for at least twenty years. Erase and programming functions have been tested to meet a typical specification of 100,000 cycles of operation. P/N:PM1315 REV. 1.2, DEC. 22, 2011 6

MX29LV160D T/B PIN CONFIGURATIONS 48 TSOP (Standard Type) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 48-Ball CSP(TFBGA/LFBGA) (Ball Pitch = 0.8 mm, Top View, Balls Facing Down, 6 x 8 mm) A13 A12 A14 A15 A16 BYTE# Q15/ A-1 GND A8 A10 A11 Q7 Q14 Q13 6 5 4 3 2 1 A9 WE# RY/ BY# A7 A3 A RE- SET# WP#/ ACC A17 A4 B A6 A2 C Q6 Q4 Q3 Q1 NC A19 Q5 Q12 VCC A18 NC Q2 Q10 Q11 A5 A1 Q0 A0 Q8 Q9 CE# OE# GND D E F G H P/N:PM1315 REV. 1.2, DEC. 22, 2011 7

MX29LV160D T/B 48-Ball WFBGA (Balls Facing Down, 4 x 6 x 0.75 mm) 6 5 4 3 2 1 A2 A4 A6 A17 NC NC WE# RE- SET# A9 A11 WP#/ ACC A1 A0 A3 A5 A7 A18 NC A10 A13 A14 A8 A12 A15 CE# Q8 Q10 Q4 Q11 A16 GND OE# Q9 A19 BYTE# Q5 Q6 Q7 Q0 Q1 Q2 Q3 VCC Q12 Q13 Q14 Q15/ A-1 GND A B C D E F G H J K L 48-Ball XFLGA (Balls Facing Down, 4 x 6 x 0.5 mm) 6 5 4 3 2 1 A2 A4 A6 A17 NC NC WE# RE- SET# A9 A11 WP#/ ACC A1 A0 A3 A5 A7 A18 NC A10 A13 A14 A8 A12 A15 CE# Q8 Q10 Q4 Q11 A16 GND OE# Q9 A19 BYTE# Q5 Q6 Q7 Q0 Q1 Q2 Q3 VCC Q12 Q13 Q14 Q15/ A-1 GND A B C D E F G H J K L P/N:PM1315 REV. 1.2, DEC. 22, 2011 8

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