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STM32F407ZGT6(芯片资料).pdf
Table 1. Device summary
1 Introduction
2 Description
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)
2.1 Full compatibility throughout the family
Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64
Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package
Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package
2.2 Device overview
Figure 5. STM32F40x block diagram
2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM
2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)
2.2.3 Memory protection unit
2.2.4 Embedded Flash memory
2.2.5 CRC (cyclic redundancy check) calculation unit
2.2.6 Embedded SRAM
2.2.7 Multi-AHB bus matrix
Figure 6. Multi-AHB matrix
2.2.8 DMA controller (DMA)
2.2.9 Flexible static memory controller (FSMC)
2.2.10 Nested vectored interrupt controller (NVIC)
2.2.11 External interrupt/event controller (EXTI)
2.2.12 Clocks and startup
2.2.13 Boot modes
2.2.14 Power supply schemes
2.2.15 Power supply supervisor
2.2.16 Voltage regulator
Figure 7. Regulator ON/internal reset OFF
Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization
Figure 9. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization
2.2.17 Real-time clock (RTC), backup SRAM and backup registers
2.2.18 Low-power modes
2.2.19 VBAT operation
2.2.20 Timers and watchdogs
Table 3. Timer feature comparison
2.2.21 Inter-integrated circuit interface (I²C)
2.2.22 Universal synchronous/asynchronous receiver transmitters (USART)
Table 4. USART feature comparison
2.2.23 Serial peripheral interface (SPI)
2.2.24 Inter-integrated sound (I2S)
2.2.25 Audio PLL (PLLI2S)
2.2.26 Secure digital input/output interface (SDIO)
2.2.27 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
2.2.28 Controller area network (bxCAN)
2.2.29 Universal serial bus on-the-go full-speed (OTG_FS)
2.2.30 Universal serial bus on-the-go high-speed (OTG_HS)
2.2.31 Digital camera interface (DCMI)
2.2.32 Random number generator (RNG)
2.2.33 General-purpose input/outputs (GPIOs)
2.2.34 Analog-to-digital converters (ADCs)
2.2.35 Temperature sensor
2.2.36 Digital-to-analog converter (DAC)
2.2.37 Serial wire JTAG debug port (SWJ-DP)
2.2.38 Embedded Trace Macrocell™
3 Pinouts and pin description
Figure 10. STM32F40x LQFP64 pinout
Figure 11. STM32F40x LQFP100 pinout
Figure 12. STM32F40x LQFP144 pinout
Figure 13. STM32F40x LQFP176 pinout
Figure 14. STM32F40x UFBGA176 ballout
Table 5. Legend/abbreviations used in the pinout table (continued)
Table 6. STM32F40x pin and ball definitions (continued)
Table 7. Alternate function mapping (continued)
4 Memory map
Figure 15. Memory map
5 Electrical characteristics
5.1 Parameter conditions
5.1.1 Minimum and maximum values
5.1.2 Typical values
5.1.3 Typical curves
5.1.4 Loading capacitor
5.1.5 Pin input voltage
Figure 16. Pin loading conditions
Figure 17. Pin input voltage
5.1.6 Power supply scheme
Figure 18. Power supply scheme
5.1.7 Current consumption measurement
Figure 19. Current consumption measurement scheme
5.2 Absolute maximum ratings
Table 8. Voltage characteristics
Table 9. Current characteristics
Table 10. Thermal characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 11. General operating conditions (continued)
Table 12. Limitations depending on the operating power supply range
5.3.2 VCAP1/VCAP2 external capacitor
Figure 20. External capacitor CEXT
Table 13. VCAP1/VCAP2 operating conditions
5.3.3 Operating conditions at power-up / power-down (regulator ON)
Table 14. Operating conditions at power-up / power-down (regulator ON)
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Table 15. Operating conditions at power-up / power-down (regulator OFF)
5.3.5 Embedded reset and power control block characteristics
Table 16. Embedded reset and power control block characteristics (continued)
5.3.6 Supply current characteristics
Table 17. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)
Table 18. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM
Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF
Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON
Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF
Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON
Table 19. Typical and maximum current consumption in Sleep mode
Table 20. Typical and maximum current consumptions in Stop mode
Table 21. Typical and maximum current consumptions in Standby mode
Table 22. Typical and maximum current consumptions in VBAT mode
Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF)
Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON)
Table 23. Switching output I/O current consumption
Table 24. Peripheral current consumption (continued)
5.3.7 Wakeup time from low-power mode
Table 25. Low-power mode wakeup timings
5.3.8 External clock source characteristics
Table 26. High-speed external user clock characteristics
Table 27. Low-speed external user clock characteristics
Figure 27. High-speed external clock source AC timing diagram
Figure 28. Low-speed external clock source AC timing diagram
Table 28. HSE 4-26 MHz oscillator characteristics
Figure 29. Typical application with an 8 MHz crystal
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)
Figure 30. Typical application with a 32.768 kHz crystal
5.3.9 Internal clock source characteristics
Table 30. HSI oscillator characteristics
Table 31. LSI oscillator characteristics
Figure 31. ACCLSI versus temperature
5.3.10 PLL characteristics
Table 32. Main PLL characteristics (continued)
Table 33. PLLI2S (audio PLL) characteristics (continued)
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
Table 34. SSCG parameters constraint
Figure 32. PLL output clock waveforms in center spread mode
Figure 33. PLL output clock waveforms in down spread mode
5.3.12 Memory characteristics
Table 35. Flash memory characteristics
Table 36. Flash memory programming
Table 37. Flash memory programming with VPP
Table 38. Flash memory endurance and data retention
5.3.13 EMC characteristics
Table 39. EMS characteristics
Table 40. EMI characteristics
5.3.14 Absolute maximum ratings (electrical sensitivity)
Table 41. ESD absolute maximum ratings
Table 42. Electrical sensitivities
5.3.15 I/O current injection characteristics
Table 43. I/O current injection susceptibility
5.3.16 I/O port characteristics
Table 44. I/O static characteristics
Table 45. Output voltage characteristics
Table 46. I/O AC characteristics (continued)
Figure 34. I/O AC characteristics definition
5.3.17 NRST pin characteristics
Table 47. NRST pin characteristics
Figure 35. Recommended NRST pin protection
5.3.18 TIM timer characteristics
Table 48. Characteristics of TIMx connected to the APB1 domain
Table 49. Characteristics of TIMx connected to the APB2 domain
5.3.19 Communications interfaces
Table 50. I2C characteristics
Figure 36. I2C bus AC waveforms and measurement circuit
Table 51. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)
Table 52. SPI characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 0
Figure 38. SPI timing diagram - slave mode and CPHA = 1(1)
Figure 39. SPI timing diagram - master mode(1)
Table 53. I2S characteristics
Figure 40. I2S slave timing diagram (Philips protocol)(1)
Figure 41. I2S master timing diagram (Philips protocol)(1)
Table 54. USB OTG FS startup time
Table 55. USB OTG FS DC electrical characteristics
Figure 42. USB OTG FS timings: definition of data signal rise and fall time
Table 56. USB OTG FS electrical characteristics
Table 57. USB FS clock timing parameters
Table 58. USB HS DC electrical characteristics
Table 59. USB HS clock timing parameters
Figure 43. ULPI timing diagram
Table 60. ULPI timing
Table 61. Ethernet DC electrical characteristics
Figure 44. Ethernet SMI timing diagram
Table 62. Dynamics characteristics: Ethernet MAC signals for SMI
Figure 45. Ethernet RMII timing diagram
Table 63. Dynamics characteristics: Ethernet MAC signals for RMII
Figure 46. Ethernet MII timing diagram
Table 64. Dynamics characteristics: Ethernet MAC signals for MII
5.3.20 12-bit ADC characteristics
Table 65. ADC characteristics (continued)
Table 66. ADC accuracy at fADC = 30 MHz
Figure 47. ADC accuracy characteristics
Figure 48. Typical connection diagram using the ADC
Figure 49. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 50. Power supply and reference decoupling (VREF+ connected to VDDA)
5.3.21 Temperature sensor characteristics
Table 67. TS characteristics
5.3.22 VBAT monitoring characteristics
Table 68. VBAT monitoring characteristics
5.3.23 Embedded reference voltage
Table 69. Embedded internal reference voltage
5.3.24 DAC electrical characteristics
Table 70. DAC characteristics (continued)
Figure 51. 12-bit buffered /non-buffered DAC
5.3.25 FSMC characteristics
Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 73. Asynchronous multiplexed PSRAM/NOR read timings
Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 74. Asynchronous multiplexed PSRAM/NOR write timings
Figure 56. Synchronous multiplexed NOR/PSRAM read timings
Table 75. Synchronous multiplexed NOR/PSRAM read timings
Figure 57. Synchronous multiplexed PSRAM write timings
Table 76. Synchronous multiplexed PSRAM write timings
Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings
Table 77. Synchronous non-multiplexed NOR/PSRAM read timings
Figure 59. Synchronous non-multiplexed PSRAM write timings
Table 78. Synchronous non-multiplexed PSRAM write timings
Figure 60. PC Card/CompactFlash controller waveforms for common memory read access
Figure 61. PC Card/CompactFlash controller waveforms for common memory write access
Figure 62. PC Card/CompactFlash controller waveforms for attribute memory read access
Figure 63. PC Card/CompactFlash controller waveforms for attribute memory write access
Figure 64. PC Card/CompactFlash controller waveforms for I/O space read access
Figure 65. PC Card/CompactFlash controller waveforms for I/O space write access
Table 79. Switching characteristics for PC Card/CF read and write cycles in attribute/common space
Table 80. Switching characteristics for PC Card/CF read and write cycles in I/O space
Figure 66. NAND controller waveforms for read access
Figure 67. NAND controller waveforms for write access
Figure 68. NAND controller waveforms for common memory read access
Figure 69. NAND controller waveforms for common memory write access
Table 81. Switching characteristics for NAND Flash read cycles
Table 82. Switching characteristics for NAND Flash write cycles
5.3.26 Camera interface (DCMI) timing specifications
Table 83. DCMI characteristics
5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics
Figure 70. SDIO high-speed mode
Figure 71. SD default mode
Table 84. SD / MMC characteristics
5.3.28 RTC characteristics
Table 85. RTC characteristics
6 Package characteristics
6.1 Package mechanical data
Figure 72. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
Figure 73. Recommended footprint(1)
Table 86. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
Figure 74. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
Figure 75. Recommended footprint(1)
Table 87. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Figure 76. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
Figure 77. Recommended footprint(1)
Table 88. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
Figure 78. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline
Table 89. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data
Figure 79. LQFP176 24 x 24 mm, 144-pin low-profile quad flat package outline
Table 90. LQFP176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data
6.2 Thermal characteristics
Table 91. Package thermal characteristics
7 Part numbering
Table 92. Ordering information scheme
Appendix A Application block diagrams
A.1 Main applications versus package
Table 93. Main applications versus package for STM32F407xx microcontrollers
A.2 Application example with regulator OFF
Figure 80. Regulator OFF/internal reset ON
Figure 81. Regulator OFF/internal reset OFF
A.3 USB OTG full speed (FS) interface solutions
Figure 82. USB controller configured as peripheral-only and used in Full speed mode
Figure 83. USB controller configured as host-only and used in full speed mode
Figure 84. USB controller configured in dual mode and used in full speed mode
A.4 USB OTG high speed (HS) interface solutions
Figure 85. USB controller configured as peripheral, host, or dual-mode and used in high speed mode
A.5 Complete audio player solutions
Figure 86. Complete audio player solution 1
Figure 87. Complete audio player solution 2
Figure 88. Audio player solution using PLL, PLLI2S, USB and 1 crystal
Figure 89. Audio PLL (PLLI2S) providing accurate I2S clock
Figure 90. Master clock (MCK) used to drive the external audio DAC
Figure 91. Master clock (MCK) not used to drive the external audio DAC
A.6 Ethernet interface solutions
Figure 92. MII mode using a 25 MHz crystal
Figure 93. RMII with a 50 MHz oscillator
Figure 94. RMII with a 25 MHz crystal and PHY with PLL
8 Revision history
Table 94. Document revision history (continued)
STM32F405xx
STM32F407xx
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Features
■ Core: ARM 32-bit Cortex™-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 168 MHz,
memory protection unit, 210 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
■ Memories
– Up to 1 Mbyte of Flash memory
– Up to 192+4 Kbytes of SRAM including 64-
Kbyte of CCM (core coupled memory) data
RAM
– Flexible static memory controller
supporting Compact Flash, SRAM,
PSRAM, NOR and NAND memories
■ LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 1.8 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
●
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
■ 3×12-bit, 2.4 MSPS A/D converters: up to 24
channels and 7.2 MSPS in triple interleaved
mode
■ 2×12-bit D/A converters
■ General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
■ Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 168 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
1. The WLCSP90 package will soon be available.
FBGA
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
WLCSP90
UFBGA176
(10 × 10 mm)
■ Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 84 MHz
– Up to 138 5 V-tolerant I/Os
■ Up to 15 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/2 UARTs (10.5 Mbit/s,
ISO 7816 interface, LIN, IrDA, modem
control)
– Up to 3 SPIs (37.5 Mbits/s), 2 with muxed
full-duplex I2S to achieve audio class
accuracy via internal audio PLL or external
clock
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
■ Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
■ 8- to 14-bit parallel camera interface up to
54 Mbytes/s
■ True random number generator
■ CRC calculation unit
■ 96-bit unique ID
■ RTC: subsecond accuracy, hardware calendar
Table 1.
Device summary
Reference
Part number
STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG
STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG,
STM32F407VE, STM32F407ZE, STM32F407IE
January 2012
Doc ID 022152 Rev 2
1/167
www.st.com
1
Contents
Contents
STM32F405xx, STM32F407xx
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2
ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 18
2.2.1
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 18
2.2.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.3
2.2.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19
2.2.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.6
2.2.7
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.8
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.9
2.2.10
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 21
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.11
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.12
2.2.13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.14
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.15
2.2.16
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 26
2.2.17
2.2.18
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.19
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.20
2.2.21
Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Universal synchronous/asynchronous receiver transmitters (USART) . 31
2.2.22
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.23
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.24
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.25
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 33
2.2.26
2.2.27
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 33
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.28
2.2.29
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 34
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STM32F405xx, STM32F407xx
Contents
3
4
5
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 34
2.2.30
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.31
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.32
2.2.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 35
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.34
2.2.35
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.36
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.37
2.2.38
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2
5.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.1
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.3
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.4
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1.6
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.2
Operating conditions at power-up / power-down (regulator ON) . . . . . . 68
5.3.3
5.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 68
Embedded reset and power control block characteristics . . . . . . . . . . . 69
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.6
5.3.7
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.9
5.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.11
PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 92
5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Contents
STM32F405xx, STM32F407xx
5.3.13
5.3.14
5.3.15
5.3.16
5.3.17
5.3.18
5.3.19
5.3.20
5.3.21
5.3.22
5.3.23
5.3.24
5.3.25
5.3.26
5.3.27
5.3.28
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 97
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 144
SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 144
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.1
6.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . 155
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 156
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 158
Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
A.1
A.2
A.3
A.4
A.5
A.6
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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List of tables
List of tables
Table 18.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1.
STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12
Table 2.
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3.
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4.
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.
STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6.
Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 7.
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 8.
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 9.
Table 10.
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 11. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 12.
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 67
Table 13.
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 14. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 68
Table 15. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 68
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 16.
Table 17.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 72
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 19.
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 20.
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 76
Table 21.
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 77
Table 22.
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23.
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 24.
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 25.
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 26.
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 27.
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 28.
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 29.
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 30.
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 31.
Table 32. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 33.
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 34.
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 35.
Table 36.
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 37.
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 38.
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 39.
Table 40.
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 41.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 42.
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 43.
Table 44.
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 45. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 46.
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of tables
STM32F405xx, STM32F407xx
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 104
Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 105
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
USB FS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 116
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 117
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 118
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 127
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 128
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 134
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Switching characteristics for PC Card/CF read and write cycles
in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 81.
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 82.
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 83.
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 84.
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 85.
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 147
Table 86.
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 148
Table 87.
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 149
Table 88.
UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . 150
Table 89.
LQFP176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 151
Table 90.
Table 91.
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 92. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 93. Main applications versus package for STM32F407xx microcontrollers . . . . . . . . . . . . . . 154
Table 94.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 80.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 9.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 14
Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Regulator ON/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 26
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 20. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 73
Figure 22. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 73
Figure 23. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 74
Figure 24. Typical current consumption vs temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 74
Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 77
Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 78
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 28.
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 31. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 33. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 34.
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 35. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 36.
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 39. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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List of figures
STM32F405xx, STM32F407xx
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 40.
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 41.
Figure 42. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 114
Figure 43. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 44. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 45. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 46. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 47. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 48. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 49. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 122
Figure 50. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 122
Figure 51.
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 127
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 128
Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 56. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 57. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 59. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 60. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 136
Figure 61. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 137
Figure 62. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 63. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 64. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 139
Figure 65. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 140
Figure 66. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 67. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 68. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 143
Figure 69. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 143
Figure 70. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 71. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 72.
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 147
Figure 73. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 74.
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 148
Figure 75. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 76.
LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 77. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 78. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline . 150
Figure 79.
LQFP176 24 x 24 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 151
Figure 80. Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 81. Regulator OFF/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 82. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 83. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 156
Figure 84. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 157
Figure 85. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 86. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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Doc ID 022152 Rev 2
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