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Application Report SLAA116 – December 2000 Mike Mitchell Using PWM Timer_B as a DAC MSP430 ABSTRACT This application report describes how to simultaneously create a sine wave, a ramp, and a dc level with pulse-width modulated (PWM) signals from Timer_B on the MSP430 ultralow power family of microcontrollers. PWM signals are often used to create analog signals in embedded applications. This report shows how to create both ac signals and dc levels with PWM outputs. The example in this report uses Timer_B on the MSP430F149, but Timer_A could also be used in a similar manner. Contents 1 2 Introduction.................................................................................................................................... 2 Theory of Operation ...................................................................................................................... 2 2.1 Resolution ................................................................................................................................. 3 2.2 Frequency ................................................................................................................................. 4 2.3 MSP430 resources used ........................................................................................................... 5 2.4 Circuit Diagram and Signals ...................................................................................................... 5 2.5 Filter Requirements................................................................................................................... 7 2.6 Adding the DC and AC Signals Together .................................................................................. 8 3 Software Listing and Description ................................................................................................. 9 3.1 DCO Calibration ...................................................................................................................... 10 Appendix A. Software Listing............................................................................................................ 12 Figures Figure 1. PWM Signal ......................................................................................................................... 2 Figure 2. PWM DAC Block Diagram................................................................................................... 3 Figure 3. Circuit Diagram ................................................................................................................... 6 Figure 4. AC Signals........................................................................................................................... 6 Figure 5. DC Signal............................................................................................................................. 7 Figure 6. Summing Circuit ................................................................................................................. 8 Figure 7. Offset Sine Wave................................................................................................................. 9 Figure 8. Software Flow.................................................................................................................... 10 1

SLAA116 1 Introduction Many embedded microcontroller applications require generation of analog signals. Sometimes an integrated or stand-alone digital-to-analog converter (DAC) is used for this purpose. However, PWM signals can often be used for generating the required analog signals. PWM signals can be used to create both dc and ac analog signals. The report below discusses using a PWM timer as a DAC and shows an example of simultaneously creating a sinusoid, a ramp, and a dc level and adding the dc level and sine wave to produce an offset ac signal. This report uses the PWM timer Timer_B. Timer_A could also be used in a similar manner. 2 Theory of Operation A PWM signal is a digital signal with fixed frequency but varying duty cycle. An example of a PWM signal is shown in Figure 1. If the duty cycle of the PWM signal is varied with time, and the PWM signal is filtered, the output of the filter will be an analog signal. The block diagram for a PWM DAC employing this technique is shown below in Figure 2. In the example code at the end of this report Timer_B on the MSP430F149 is used to simultaneously generate a sinusoid and a ramp waveform of different frequencies, and a dc level. PWM DACS can also be used to generate other signals. In fact, some speech processors from Texas Instruments, Inc. utilize PWM signals to generate speech for their applications. Fixed P eriod V ariable Duty Cycle Figure 1. PWM Signal 2 Using PWM Timer_B as a DAC

SLAA116 M SP 430 m icrocontroller P W M output Analog Filter Figure 2. PWM DAC Block Diagram 2.1 Resolution The resolution of a PWM DAC constructed with Timer_B is simply equivalent to the length of the counter, which is usually the value placed in CCR0. The LSB of the PWM DAC is one count and the resolution is the total number of counts: R COUNTS = L COUNTS RCOUNTS = Resolution in counts LCOUNTS = Length of counter in counts For example, this report implements an 8-bit DAC, so the length of the counter is 8-bits, or 256 counts. In more general terms, the resolution of a PWM DAC constructed with a PWM timer and a filter is equivalent to the resolution of the PWM signal used to create the DAC. The resolution of the PWM signal is then dependant on the length of the counter and the smallest duty-cycle change the PWM counter is capable of making. The resolution is expressed mathematically as: RCOUNTS = L C RCOUNTS = Resolution in counts L = Length of counter in counts C = Smallest duty-cycle change in counts Expressed as number of bits the resolutions is calculated as: Using PWM Timer_B as a DAC 3

SLAA116 R BITS = Log 2 ( R COUNTS ) = Log 2 = L C Or R BITS = Log 2 ( R COUNTS ) = ln( ) R COUNTS )2ln( ) ln( L C )2ln( For example, if a PWM counter has a length of 512 counts and can vary the duty cycle by a minimum of 2 counts, the resolution in counts of the resulting PWM DAC would be: RCOUNTS = L C = 512 = 2 256 And the resolution in bits would be RBITS = Log 2 ( 256 ) = ) 256 ln( )2ln( = 8 bits 2.2 Frequency The frequency required for the PWM output signal is equivalent to the update rate of the DAC, since each change in PWM duty cycle is the equivalent of one DAC sample. The frequency required for the PWM timer will depend on the required PWM signal frequency and the desired resolution. It is shown as: = F clock F PWM n x 2 where: Fclock is the required PWM timer frequency FPWM is the PWM signal frequency, which is the DAC update rate n is the desired resolution of the DAC in bits This report shows how to construct an 8-bit PWM DAC and how to simultaneously generate a 250Hz sine wave and a 125Hz ramp. The desired sampling rate for this example is 8KHz (32 samples for each sine wave cycle (16x oversampled), and 64 samples for each ramp cycle (32x oversampled). This results in a required PWM signal frequency of 8KHz and a required PWM clock frequency of 2.048MHz. It is usually best for the PWM signal frequency to be much higher than the desired sine wave frequency or the desired bandwidth of signals to be produced. Generally, the higher the PWM frequency the lower the order of filter required and the easier it is to build a suitable filter. 4 Using PWM Timer_B as a DAC ł Ł

2.3 MSP430 resources used SLAA116 The example code at the end of this report shows how to simultaneously generate a 250Hz sine wave, a 125Hz ramp, and a 2/3 Vcc dc value using Timer_B and external filters. Timer_A could be used in a similar manner. Timer_B is used in the 16-bit mode, but is configured to operate in up mode where the counter counts up to the contents of capture/compare register 0 (CCR0) and then restarts at zero. CCR0 is loaded with 255 therefore giving the counter an effective 8-bit length. CCR1 and output TB1 are used for the sine wave. CCR2 and TB2 are used for the ramp, and CCR3 and TB3 are used for the dc value. For each output, the output mode is selected to be mode 7, or reset/set mode. In this mode, each output is reset when the counter reaches the respective CCRx value and is set when the counter reaches the CCR0 value. This provides positive pulses equivalent to the value in CCRx on each respective output. Finally, SMCLK is used as the clock source for Timer_B. Other resources include: • 32768Hz crystal oscillator • On-chip digitally controlled oscillator (DCO) operating at 2.048MHz • SMCLK and MCLK operating at 2.048MHz • • Timer_A used to calibrate the DCO Two CPU registers 2.4 Circuit Diagram and Signals The complete circuit diagram used for this example is shown below in Figure 3. The ac signals produced by this example are shown in Figure 4. The dc value produced in this example is shown in Figure 5 together with its PWM signal. Using PWM Timer_B as a DAC 5

SLAA116 V cc 32768Hz MSP430F149IPM DV cc AV cc XIN P4.1/TB1 XOUT/TCLK P4.2/TB2 DV SS AV SS P4.3/TB3 R1=2K R2= 1M C1=.1µF C2 = 200pF 200pF 2K .1µF 330K .05µF 1M DC Figure 3. Circuit Diagram Figure 4. AC Signals 6 Using PWM Timer_B as a DAC

SLAA116 Figure 5. DC Signal The sine wave produced by this example used 32 samples per cycle. The sample values are contained in a table at the beginning of the program. A pointer is used to point to the next value of the sine table so that at the end of each PWM cycle, the new value of the sine wave is written to the capture/compare register of the PWM timer. The ramp in this example does not require a table of data values. Rather, it was generated by simply incrementing the duty-cycle each cycle of the PWM signal until the maximum was reached and then starting over at the minimum duty-cycle. This gradual increase in PWM signal duty-cycle results in a ramp voltage when it is filtered. The dc level in this example was set by simply setting the value of the PWM signal duty-cycle and never changing it. The dc level is directly proportional to the value of the duty-cycle of the PWM signal. So, since the duty-cycle of the PWM signal on TB3 does not change, when it is filtered by the RC network, a dc value results. 2.5 Filter Requirements The reconstruction filters used for each signal in this example are shown above in Figure 3. The filter for the ac signals is a simple two-pole stacked-RC filter. It was chosen for it’s simplicity and lack of active components for low power designs. This necessitates a higher sampling rate than would be required if the filter were a higher order. With the type of filter shown above, it is recommended to use at least 16x oversampling for the DAC. The cutoff frequency of the filter can be calculated by: Using PWM Timer_B as a DAC 7

SLAA116 = FC 1 RC p2 where 11 CR = CR 22 = RC The filter gives better response when R2 >> R1. Also, setting the cutoff frequency too close to the bandwidth edge will cause a fair amount of attenuation. To reduce the amount of attenuation caused by the filter, set the cutoff frequency above the bandwidth edge, but << than the frequency of the PWM signal. The filter used for the dc value is used for charge storage rather than ac signal filtering. Therefore, a simple, single-pole RC filter is used. 2.6 Adding the DC and AC Signals Together The signals produced by the PWM DAC may be added together. The circuit in Figure 6 shows the dc offset of 2/3 Vcc being added to the sine wave to produce an offset sine wave. In addition, the sine wave was attenuated by approximately 2/3 to allow it to be moved up or down on the dc offset without clipping the summing amplifier. This produced the 1VPP sine wave sitting on a dc offset of approximately 2V shown below in Figure 7. The PWM signal is shown in the background for reference. V cc MSP430F149IPM DV cc AV cc XIN P4.1/TB1 XOUT/TCLK 680 33K .2µF .05µF 10K - + TLV2771 Offset Sine 32768Hz P4.3/TB3 330K .05µF DV SS AV SS Figure 6. Summing Circuit 8 Using PWM Timer_B as a DAC

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