Technical Report
LGDP4535 Application Notes
240 x 320 Resolution and 260K color Single Chip Solution
LG Electronics
System IC Team
LDI Circuit Design Gr.
GS Gangnam Tower
In SEOUL
2008 MAR 10
Version 2.0
240x320 Resolution and 260K color Single Chip Solution
◈ INDEX
LGDP4535
1. LG Display 2.8” QVGA Panel
1) Application Circuit
2) Initial code
2. HYDIS 2.8” QVGA Panel
1) Application Circuit
2) Initial code
240x320 Resolution and 260K color Single Chip Solution
◈ LG Display 2.8” Application Circuit
LGDP4535
240x320 Resolution and 260K color Single Chip Solution
◈ Hydis 2.8” Application Circuit
LGDP4535
Gamma Setting - LGDP4535 / LG Display 2.8-inch QVGA module
Initial Code - LGDP4535 / LG Display 2.8"
2008-03-10
* Condition
1. VCI = VCC = IOVCC = 2.8V
2. R90 [DIVI] = "01" => 1/2 division
Initialization
Reg (Hex) Data (Hex) Delay (ms)
0X15
0x9A
0X11
0X10
0X12
0X13
DELAY
0X12
DELAY
0X10
0X13
DELAY
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X01
0X02
0X03
0X08
0X0A
0X60
0X61
0X90
0X92
0X93
0XA0
0XA3
0X07
0X07
0X07
0X07
0X07
0X0030
0X0010
0X0020
0X3428
0X0002
0X1038
0X0012
0X3420
0X3038
0X0000
0X0402
0X0307
0X0304
0X0004
0X0401
0X0707
0X0305
0X0610
0X0610
0X0100
0X0300
0X1030
0X0808
0X0008
0X2700
0X0001
0X013E
0X0100
0X0100
0X3000
0X0010
0X0001
0X0021
0X0023
0X0033
0X0133
SLEEP ON
↔
SLEEP EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
0X07
0X0032
0X10
0X0008
40
40
70
DELAY
0X07
0X0022
DELAY
Power ON sequence
0X07
0X0002
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
0X0001
0X0000
0X0000
0X0008
20
20
20
10
↓
Power ON sequence
↓
Display ON sequence
DELAY
10
0X10
0X000A
STAND-BY ON
↔
STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
0X07
0X0032
DELAY
0X07
0X0022
Display Mode
DELAY
&
0X07
0X0002
Gamma settings
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
0X0001
0X0000
0X0000
0X0008
20
20
20
10
0X00
0X10
DELAY
0X0001
0X0008
↓
10
Power ON sequence
↓
Display ON sequence
DELAY
10
0X10
0X0009
DEEP STAND-BY ON
↔
DEEP STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
Display ON sequence
0X07
0X0032
DELAY
0X07
0X0022
DELAY
0X07
0X0002
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
DELAY
0X10
0X0001
0X0000
0X0000
0X0008
0X000C
20
20
20
10
10
2 times CS pin toggle
DELAY
1
4 times CS pin toggle
Initialization
or
↔ STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
H/W Reset
Initialization
Gamma Setting - LGDP4535 / Hydis 2.8-inch QVGA module
Initial Code - LGDP4535 / Hydis 2.8"
2008-03-10
* Condition
1. VCI = VCC = IOVCC = 2.8V
2. R90 [DIVI] = "01" => 1/2 division
Initialization
Reg (Hex) Data (Hex) Delay (ms)
0X15
0x9A
0X11
0X10
0X12
0X13
DELAY
0X12
DELAY
0X10
0X13
DELAY
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X01
0X02
0X03
0X08
0X0A
0X60
0X61
0X90
0X92
0X93
0XA0
0XA3
0X07
0X07
0X07
0X07
0X07
0X0030
0X0010
0X0020
0X3428
0X0004
0X1050
0X0014
0X3420
0X3050
0X0003
0X0305
0X0004
0X0304
0X0004
0X0303
0X0606
0X0403
0X050F
0X0510
0X0100
0X0300
0X1030
0X0808
0X0008
0X2700
0X0001
0X013E
0X010F
0X0001
0X3000
0X0010
0X0001
0X0021
0X0023
0X0033
0X0133
SLEEP ON
↔
SLEEP EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
0X07
0X0032
0X10
0X0008
40
40
70
DELAY
0X07
0X0022
DELAY
Power ON sequence
0X07
0X0002
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
0X0001
0X0000
0X0000
0X0008
20
20
20
10
↓
Power ON sequence
↓
Display ON sequence
DELAY
10
0X10
0X000A
STAND-BY ON
↔
STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
0X07
0X0032
DELAY
0X07
0X0022
Display Mode
DELAY
&
0X07
0X0002
Gamma settings
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
0X0001
0X0000
0X0000
0X0008
20
20
20
10
0X00
0X10
DELAY
0X0001
0X0008
↓
10
Power ON sequence
↓
Display ON sequence
DELAY
10
0X10
0X0009
DEEP STAND-BY ON
↔
DEEP STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
Reg (Hex) Data (Hex) Delay (ms)
Display ON sequence
0X07
0X0032
DELAY
0X07
0X0022
DELAY
0X07
0X0002
DELAY
0x07
0X0000
DELAY
0X17
0x13
0X12
0X10
DELAY
0X10
0X0001
0X0000
0X0000
0X0008
0X000C
20
20
20
10
10
2 times CS pin toggle
DELAY
1
4 times CS pin toggle
Initialization
or
↔ STAND-BY EXIT
Reg (Hex) Data (Hex) Delay (ms)
H/W Reset
Initialization