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NT35510 data sheet.pdf

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    NT35510 One-chip Driver IC with internal GRAM for 16.7M colors 480RGB x 864 a-Si TFT LCD with CPU / RGB / MIPI / MDDI Interface or without internal CGRAM for 16.7M colors 480RGB x 1024 a-Si TFT LCD with RGB Interface V0.05 Preliminary Á Љꗬꗬ 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 1
    PRELIMINARY NT35510 REVISION HISTORY................................................................................................................................................8 1 DESCRIPTION ....................................................................................................................................................11 1.1 PURPOSE OF THIS DOCUMENT .............................................................................................................................11 1.2 GENERAL DESCRIPTION ......................................................................................................................................11 2 FEATURES .........................................................................................................................................................12 3 BLOCK DIAGRAM..............................................................................................................................................14 4 PIN DESCRIPTION .............................................................................................................................................15 4.1 POWER SUPPLY PINS..........................................................................................................................................15 4.2 80-SYSTEM INTERFACE PINS...............................................................................................................................16 4.3 SPI /I2C INTERFACE PINS ...................................................................................................................................16 4.4 RGB INTERFACE PINS ........................................................................................................................................17 4.5 MIPI/MDDI INTERFACE PINS...............................................................................................................................18 4.6 INTERFACE LOGIC PINS.......................................................................................................................................19 4.7 DRIVER OUTPUT PINS .........................................................................................................................................21 4.8 DC/DC CONVERTER PINS ...................................................................................................................................22 4.9 LABC AND CABC CONTROL PINS ...............................................................................................................24 4.10 TEST PINS .....................................................................................................................................................25 5 FUNCTIONAL DESCRIPTION............................................................................................................................26 5.1 MPU INTERFACE.................................................................................................................................................26 5.1.1 Interface Type Selection .......................................................................................................................................26 5.1.2 80-series MPU Interface........................................................................................................................................27 5.1.3 Serial Interface.......................................................................................................................................................45 5.2 I2C INTERFACE...................................................................................................................................................54 5.2.1 Slave Address of I2C.............................................................................................................................................55 5.2.2 Register Write Sequence of I2C Interface ...........................................................................................................55 5.2.3 RAM Data Write Sequence of I2C Interface.........................................................................................................55 5.2.4 Register Read Sequence of I2C Interface ...........................................................................................................59 5.2.5 RAM Data Read Sequence of I2C Interface.........................................................................................................59 5.3 MIPI INTERFACE .................................................................................................................................................63 5.3.1 Display Module Pin Configuration for DSI ..........................................................................................................64 5.3.2 Display Serial Interface (DSI) ...............................................................................................................................65 5.3.3 Memory Write/Read Format................................................................................................................................151 5.3.4 System Power-Up and Initialization...................................................................................................................158 5.4 MDDI INTERFACE .............................................................................................................................................159 5.4.1 MDDI Link Protocol by The NT35510.................................................................................................................160 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 2
    PRELIMINARY NT35510 5.4.2 MDDI Link Packet Descriptions by the NT35510 ..............................................................................................161 5.4.3 Writing Video Data to Memory Sequence..........................................................................................................171 5.4.4 Writing Register Sequence.................................................................................................................................171 5.4.5 Reading Video Data from Memory Sequence ...................................................................................................172 5.4.6 Reading Register Sequence...............................................................................................................................172 5.4.7 Hibernation Setting .............................................................................................................................................173 5.4.8 MDDI Deep Standby Mode Setting.....................................................................................................................174 5.5 INTERFACE PAUSE ............................................................................................................................................176 5.6 DATA TRANSFER BREAK AND RECOVERY ..........................................................................................................177 5.7 DISPLAY MODULE DATA TRANSFER MODES.......................................................................................................179 5.8 RGB INTERFACE...............................................................................................................................................180 5.8.1 General Description ............................................................................................................................................180 5.8.2 RGB Interface Timing Chart ...............................................................................................................................181 5.8.3 RGB Interface Mode Set .....................................................................................................................................182 5.8.4 RGB Interface Bus Width Set .............................................................................................................................186 5.9 FRAME MEMORY...............................................................................................................................................190 5.9.1 Configuration.......................................................................................................................................................190 5.9.2 Address Counter .................................................................................................................................................191 5.9.3 Interface to Memory Write Direction..................................................................................................................192 5.9.4 Frame Memory to Display Address Mapping....................................................................................................193 5.10 TEARING EFFECT INFORMATION.......................................................................................................................194 5.10.1 Tearing Effect Output Line ...............................................................................................................................194 5.10.2 Tearing Effect Bus Trigger................................................................................................................................199 5.11 CHECKSUM.....................................................................................................................................................211 5.12 POWER ON/OFF SEQUENCE ............................................................................................................................213 5.12.1 Case 1 – RESX line is held High or Unstable by Host at Power On..............................................................214 5.12.2 Case 2 – RESX line is held Low by host at Power On....................................................................................215 5.12.3 Uncontrolled Power Off ....................................................................................................................................215 5.13 POWER LEVEL MODES ....................................................................................................................................216 5.13.1 Definition............................................................................................................................................................216 5.13.2 Power Level Mode Flow Chart..........................................................................................................................217 5.14 RESET FUNCTION ............................................................................................................................................219 5.14.1 Register Default Value ......................................................................................................................................219 5.14.2 Output or Bi-directional (I/O) Pins ...................................................................................................................221 5.14.3 Input Pins...........................................................................................................................................................221 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 3
    PRELIMINARY NT35510 5.15 SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ......................................222 5.15.1 Register loading Detection...............................................................................................................................222 5.15.2 Functionality Detection.....................................................................................................................................223 5.15.3 Chip Attachment Detection ..............................................................................................................................224 5.16 DISPLAY PANEL COLOR CHARACTERISTICS .....................................................................................................225 5.17 GAMMA FUNCTION ..........................................................................................................................................226 5.18 BASIC DISPLAY MODE.....................................................................................................................................227 5.19 INSTRUCTION SETTING SEQUENCE...................................................................................................................228 5.19.1 Sleep In/Out Sequence .....................................................................................................................................228 5.19.2 Deep Standby Mode Enter/Exit Sequence.......................................................................................................229 5.20 INSTRUCTION SETUP FLOW .............................................................................................................................230 5.20.1 Initializing with the Built-in Power Supply Circuits........................................................................................230 5.20.2 Power OFF Sequence .......................................................................................................................................231 5.21 MTP WRITE SEQUENCE ..................................................................................................................................232 5.22 DYNAMIC BACKLIGHT CONTROL FUNCTION......................................................................................................233 5.22.1 PWM Control Architecture................................................................................................................................235 5.22.2 Dimming Function for LABC and Manual Brightness Control ......................................................................240 5.22.3 Dimming Function for CABC and Force PWM Function................................................................................243 5.22.4 PWM Signal Setting for CABC and LABC .......................................................................................................244 5.22.5 Content Adaptive Brightness Control (CABC)................................................................................................246 5.22.6 Ambient Light Sensor and Automatic Brightness Control (LABC)...............................................................247 5.23 COLUMN, 1-DOT, 2-DOT, 3-DOT AND 4-DOT INVERSION (VCOM DC DRIVE).....................................................254 6 COMMAND DESCRIPTIONS ...........................................................................................................................255 6.1 USER COMMAND SET........................................................................................................................................255 NOP (0000h)..................................................................................................................................................................259 SWRESET: Software Reset (0100h) ............................................................................................................................260 RDDID: Read Display ID (0400h~0402h).....................................................................................................................261 RDNUMED: Read Number of Errors on DSI (0500h)..................................................................................................262 RDDPM: Read Display Power Mode (0A00h) .............................................................................................................263 RDDMADCTL: Read Display MADCTL (0B00h)..........................................................................................................264 RDDCOLMOD: Read Display Pixel Format (0C00h) ..................................................................................................265 RDDIM: Read Display Image Mode (0D00h) ...............................................................................................................266 RDDSM: Read Display Signal Mode (0E00h) .............................................................................................................267 RDDSDR: Read Display Self-Diagnostic Result (0F00h)...........................................................................................268 SLPIN: Sleep In (1000h) ...............................................................................................................................................269 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 4
    PRELIMINARY NT35510 SLPOUT: Sleep Out (1100h).........................................................................................................................................271 PTLON: Partial Display Mode On (1200h) ..................................................................................................................273 NORON: Normal Display Mode On (1300h)................................................................................................................274 INVOFF: Display Inversion Off (2000h).......................................................................................................................275 INVON: Display Inversion On (2100h).........................................................................................................................276 ALLPOFF: All Pixel Off (2200h) ...................................................................................................................................277 ALLPON: All Pixel On (2300h) .....................................................................................................................................279 GAMSET: Gamma Set (2600h).....................................................................................................................................281 DISPOFF: Display Off (2800h) .....................................................................................................................................282 DISPON: Display On (2900h) .......................................................................................................................................283 CASET: Column Address Set (2A00h~2A03h) ...........................................................................................................284 RASET: Row Address Set (2B00h~2B03h).................................................................................................................286 RAMWR: Memory Write (2C00h) .................................................................................................................................288 RAMRD: Memory Read (2E00h) ..................................................................................................................................289 PTLAR: Partial Area (3000h~3003h)............................................................................................................................290 TEOFF: Tearing Effect Line OFF (3400h)....................................................................................................................293 TEON: Tearing Effect Line ON (3500h) .......................................................................................................................294 MADCTL: Memory Data Access Control (3600h).......................................................................................................295 IDMOFF: Idle Mode Off (3800h) ...................................................................................................................................298 IDMON: Idle Mode On (3900h) .....................................................................................................................................299 COLMOD: Interface Pixel Format (3A00h)..................................................................................................................301 RAMWRC: Memory Write Continue (3C00h) ..............................................................................................................302 RAMRDC: Memory Read Continue (3E00h) ...............................................................................................................303 STESL: Set Tearing Effect Scan Line (4400h~4401h)................................................................................................304 GSL: Get Scan Line (4500h~4501h)............................................................................................................................306 DPCKRGB: Display Clock in RGB Interface (4A00h) ................................................................................................307 DSTBON: Deep Standby Mode On (4F00h) ................................................................................................................308 WRPFD: Write Profile Value for Display (5000h~500Fh) ...........................................................................................309 WRDISBV: Write Display Brightness (5100h) ............................................................................................................310 RDDISBV: Read Display Brightness (5200h) ............................................................................................................. 311 WRCTRLD: Write CTRL Display (5300h) ....................................................................................................................312 RDCTRLD: Read CTRL Display Value (5400h)...........................................................................................................314 WRCABC: Write Content Adaptive Brightness Control (5500h) ..............................................................................316 RDCABC: Read Content Adaptive Brightness Control (5600h) ...............................................................................317 WRHYSTE: Write Hysteresis (5700h~573Fh) .............................................................................................................318 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 5
    PRELIMINARY NT35510 WRGAMMSET: Write Gamma Setting (5800h~5807h) ...............................................................................................320 RDFSVM: Read FS Value MSBs (5A00h) ....................................................................................................................322 RDFSVL: Read FS Value LSBs (5B00h)......................................................................................................................323 RDMFFSVM: Read Median Filter FS Value MSBs (5C00h) ........................................................................................324 RDMFFSVL: Read Median Filter FS Value LSBs (5D00h)..........................................................................................325 WRCABCMB: Write CABC minimum brightness (5E00h).........................................................................................326 RDCABCMB: Read CABC minimum brightness (5F00h) ..........................................................................................327 WRLSCC: Write Light Sensor Compensation Coefficient Value (6500h~6501h) ....................................................328 RDLSCCM: Read Light Sensor Compensation Coefficient Value MSBs (6600h) ...................................................329 RDLSCCL: Read Light Sensor Compensation Coefficient Value LSBs (6700h) .....................................................330 RDBWLB: Read Black/White Low Bits (7000h)..........................................................................................................331 RDBkx: Read Bkx (7100h) ...........................................................................................................................................332 RDBky: Read Bky (7200h) ...........................................................................................................................................333 RDWx: Read Wx (7300h)..............................................................................................................................................334 RDWy: Read Wy (7400h)..............................................................................................................................................335 RDRGLB: Read Red/Green Low Bits (7500h) ............................................................................................................336 RDRx: Read Rx (7600h) ...............................................................................................................................................337 RDRy: Read Ry (7700h) ...............................................................................................................................................338 RDGx: Read Gx (7800h)...............................................................................................................................................339 RDGy: Read Gy (7900h)...............................................................................................................................................340 RDBALB: Read Blue/AColor Low Bits (7A00h) .........................................................................................................341 RDBx: Read Bx (7B00h)...............................................................................................................................................342 RDBy: Read By (7C00h)...............................................................................................................................................343 RDAx: Read Ax (7D00h)...............................................................................................................................................344 RDAy: Read Ay (7E00h) ...............................................................................................................................................345 RDDDBS: Read DDB Start (A100h~A104h) ................................................................................................................346 RDDDBC: Read DDB Continue (A800h~A804h).........................................................................................................348 RDFCS: Read First Checksum (AA00h) .....................................................................................................................350 RDCCS: Read Continue Checksum (AF00h)..............................................................................................................351 RDID1: Read ID1 Value (DA00h)..................................................................................................................................352 RDID2: Read ID2 Value (DB00h)..................................................................................................................................353 RDID3: Read ID3 Value (DC00h)..................................................................................................................................354 7 SPECIFICATIONS.............................................................................................................................................355 7.1 ABSOLUTE MAXIMUM RATINGS..........................................................................................................................355 7.2 ESD PROTECTION LEVEL..................................................................................................................................355 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 6
    PRELIMINARY NT35510 7.3 LATCH-UP PROTECTION LEVEL .........................................................................................................................355 7.4 LIGHT SENSITIVITY............................................................................................................................................355 7.5 DC CHARACTERISTICS......................................................................................................................................356 7.5.1 Basic Characteristics..........................................................................................................................................356 7.5.2 MIPI Characteristics............................................................................................................................................358 7.5.3 MDDI Characteristics ..........................................................................................................................................360 7.6 AC CHARACTERISTICS......................................................................................................................................361 7.6.1 Parallel Interface Characteristics (80-Series MCU) ..........................................................................................361 7.6.2 Serial Interface Characteristics..........................................................................................................................362 7.6.3 I2C Bus Timing Characteristics .........................................................................................................................363 7.6.4 RGB Interface Characteristics ...........................................................................................................................364 7.6.5 MIPI DSI Timing Characteristics ........................................................................................................................365 7.6.6 MDDI Timing Characteristics..............................................................................................................................369 7.6.7 Reset Input Timing..............................................................................................................................................370 8 REFERENCE APPLICATIONS.........................................................................................................................371 8.1 MICROPROCESSOR INTERFACE..........................................................................................................................371 8.2 CONNECTIONS WITH PANEL...............................................................................................................................376 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 7
    REVISION HISTORY PRELIMINARY NT35510 Checked Approved by Date Prepare d by Kevin by SW Dennis 2010/02/12 Kevin SW Dennis 2010/03/17 Version 0.00 0.01 Contents Original - Page 9, remove 320RGB x 480 - Page 10, Features, remove 320RGB x 480 and MUX description VGHO VGLO for gate control signals, remove VDDIM/VSSIM - Page11, update power voltage range - Page12, Block diagram - Page 13 to 22 : Add : VDD_DET,DIOPWR,PSWAP,DSWAP ,VGHO,VGLO,VRGH, VREFCP,CSP,CSN,LVGL,C61P,C61N,VRGH, VREF,GOUT, Remove : VDDIM/VSSIM, VDDEL Update : MVDDL,VGL,VGH,Test pins - Page23, update IF table - Page 51 to 66 : update SPI,IM3= 1 setting in figure - Page102,103, change DSIM, DSIG bit Reg to 0xB100 - Page115,124 Add WRPFD 50h on table - Page201,modified to 480x864 memory - Page202,Remove 320x480 - Page204, update whole Frame memory table - Page205, TE map to 480 lines, DOPCTR change to B100h - Page207, tvdl TBD - Page225,226,update VDD in figure - Page227,Modes to 7 - Page232,Sout update to Gout - Page235,Add chip attachment Detection section - Page237, update Gamma Structure - Page255,270,update FOSC, Example - Page266,update KB_CLED - Page272, Add inversion section - Page273,274, Power Architecture - Page275, update DIOPWR,VREFCP,VGMP1,VGLO - Page276,updateC61P/N,LVGL,VGLO,VRGH,VREFCP,DIOPWR, VGMP1/2,VGMN,VGSP,VGSN, - Page291, change name to RAMKP - Page306 to 312,remove 320x 480 resolution setting - Page337, 5400h Cmd add A and G bit - Page385, Absolute Max Rating for MV HV, remove VDDIM - Page386, VDDIM remove - Page387, Vdev value modified - Page402,403, Remove MVDDI in note - Page406, Remove 320 x 480, update 360x640 Sout sequence - Page173 to 181,MDDI windowless packet - Page377,379, A1,A8 cmd update - Page387 to 396, VDDI to 3.3V - Page362 to 376 70h to 7Eh cmd default value - Page28,29,30,40,41,42 MPU figure update - Page 12,274 Block and power architecture update 10/18/2010 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Version 0.05 8
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