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K4S640832K K4S641632K Synchronous DRAM 64Mb K-die SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K Revision History Revision 0.0 0.1 0.2 0.3 1.0 1.1 Month January March April July September February Synchronous DRAM History Year 2005 2005 2005 2005 2005 2006 - Target spec release - Change DC current - Delete bit organization for x4 - Delete 7ns speed bin - Final spec release - Added 5ns speed bin for x16 2 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K 2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Burst read single-bit write operation • DQM (x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K cycle) • Pb/Pb-free Package • RoHS compliant for Pb-free Package GENERAL DESCRIPTION The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. Ordering Information Part No. K4S640832K-T(U)C/L75 K4S641632K-T(U)C/L50 K4S641632K-T(U)C/L60 K4S641632K-T(U)C/L75 Orgainization 8Mb x 8 4Mb x 16 Max Freq. 133MHz(CL=3) 200MHz(CL=3) 166MHz(CL=3) 133MHz(CL=3) Interface Package LVTTL 54pin TSOP(II) Pb (Pb-free) Organization Row Address Column Address 8Mx8 4Mx16 A0~A11 A0~A11 A0-A8 A0-A7 Row & Column address configuration 3 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K Package Physical Dimension #54 #1 #28 #27 0 2 . 0 ± 6 7 . 1 1 8 0 0 . 0 ± 3 6 4 . 0 Synchronous DRAM 0~8°C 0.25 TYP 0.010 6 1 . 0 1 0 0 4 . 0 5 7 . 0 ~ 5 4 . 0 0 3 0 . 0 ~ 8 1 0 . 0 +0.075 0.125 -0.035 +0.003 0.005 -0.001 0 2 0 0 5 ) ( 0 . 0 . 22.62 MAX 0.891 22.22 0.875 ± 0.10 ± 0.004 0.10 MAX 0.004 0.71 ( ) 0.028 0.30 0.012 +0.10 -0.05 +0.004 -0.002 0.80 0.0315 0.21 0.008 ± 0.05 ± 0.002 1.00 0.039 ± 0.10 ± 0.004 1.20 MAX 0.047 0.05 MIN 0.002 54Pin TSOP(II) Package Dimension 4 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K FUNCTIONAL BLOCK DIAGRAM Bank Select R e f r e s h C o u n e r t R o w B u f f e r L R A S L C B R CLK ADD A d d r e s s R e g s t e r i LCKE Synchronous DRAM LWE LDQM DQi I / O C o n t r o l O u t p u t B u f f e r Data Input Register 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 S e n s e A M P Column Decoder Latency & Burst Length Programming Register R o w D e c o d e r C o l . B u f f e r LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM Samsung Electronics reserves the right to change products or specification without notice. * 5 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K PIN CONFIGURATION (Top view) x8 VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD PIN FUNCTION DESCRIPTION x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD Pin Name CLK CS CKE System clock Chip select Clock enable A0 ~ A11 Address BA0 ~ BA1 Bank select address RAS CAS WE DQM Row address strobe Column address strobe Write enable Data input/output mask DQ0 ~ N VDD/VSS Data input/output Power supply/ground VDDQ/VSSQ Data output power/ground N.C/RFU No connection /reserved for future use Synchronous DRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 x8 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. 6 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Synchronous DRAM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V °C W mA Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Min 3.0 2.0 -0.3 2.4 - -10 Typ 3.3 3.0 0 - - - Symbol VDD, VDDQ VIH VIL VOH VOL ILI Max 3.6 VDD+0.3 0.8 - 0.4 10 Unit V V V V V uA Note 1 2 IOH = -2mA IOL = 2mA 3 Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Clock RAS, CAS, WE, CS, CKE, DQM Address (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15) Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note 7 of 14 Rev. 1.1 February 2006

K4S640832K K4S641632K DC CHARACTERISTICS (x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x8) Parameter Symbol Test Condition Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current ICC4 ICC5 ICC6 ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA Input signals are changed one time during 20ns ICC2P CKE ≤ VIL(max), tCC = 10ns ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC3P CKE ≤ VIL(max), tCC = 10ns ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable Input signals are changed one time during 20ns Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V C L Synchronous DRAM Version 75 55 1 1 15 6 3 3 30 25 80 85 1 400 Unit Note mA mA mA mA mA mA mA mA uA 1 1 2 3 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S640832K-T(U)C 4. K4S640832K-T(U)L 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) 8 of 14 Rev. 1.1 February 2006

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