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SN74LVC1G00(芯片资料).pdf

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    SN74LVC1G00 www.ti.com SCES212V –APRIL 1999–REVISED FEBRUARY 2010 SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 1FEATURES • Available in the Texas Instruments NanoStar™ Package Inputs Accept Voltages to 5.5 V • Supports 5-V VCC Operation • • Max tpd of 3.8 ns at 3.3 V • Low Power Consumption, 10-mA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) ORDERING INFORMATION(1) NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) –40°C to 85°C SOT (SOT-23) – DBV SOT (SC-70) – DCK SOT (SOT-553) – DRL SN74LVC1G00YZPR _ _ _ CA_ Reel of 3000 SN74LVC1G00DBVR Reel of 250 SN74LVC1G00DBVT Reel of 3000 SN74LVC1G00DCKR Reel of 250 SN74LVC1G00DCKT Reel of 4000 SN74LVC1G00DRLR C00_ CA_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2010, Texas Instruments Incorporated See mechanical drawings for dimensions.DBV PACKAGE(TOPVIEW)51VCCA2B34GNDYDRL PACKAGE(TOPVIEW)2BVCC51A34GNDGNDYDCK PACKAGE(TOPVIEW)2B34GNDVCC5AY1YZP PACKAGE(BOTTOMVIEW)2BVCC15AGND43Y
    SN74LVC1G00 SCES212V –APRIL 1999–REVISED FEBRUARY 2010 www.ti.com FUNCTION TABLE INPUTS OUTPUT A H L X B H X L Y L H H LOGIC DIAGRAM (POSITIVE LOGIC) ABSOLUTE MAXIMUM RATINGS(1) over operating free-air temperature range (unless otherwise noted) VCC VI VO VO IIK IOK IO qJA Tstg Supply voltage range Input voltage range Voltage range applied to any output in the high-impedance or power-off state (2) Voltage range applied to any output in the high or low state (2) (3) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND VI < 0 VO < 0 Package thermal impedance (4) Storage temperature range DBV package DCK package DRL package YZP package MIN –0.5 –0.5 –0.5 –0.5 –65 MAX 6.5 6.5 6.5 VCC + 0.5 –50 –50 ±50 ±100 206 252 142 132 150 UNIT V V V V mA mA mA mA °C/W °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD 51-7. 2 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G00
    www.ti.com SCES212V –APRIL 1999–REVISED FEBRUARY 2010 RECOMMENDED OPERATING CONDITIONS(1) SN74LVC1G00 VCC Supply voltage VIH High-level input voltage VIL VI VO Low-level input voltage Input voltage Output voltage IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN 1.65 1.5 0.65 × VCC 1.7 2 0.7 × VCC MAX UNIT 5.5 V V V V V 0.35 × VCC 0.7 0.8 0.3 × VCC 5.5 VCC –4 –8 –16 mA –24 –32 4 8 16 mA 24 32 20 10 5 85 ns/V °C 0 0 –40 (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN74LVC1G00
    SN74LVC1G00 SCES212V –APRIL 1999–REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TYP(1) MAX UNIT IOH = –100 mA IOH = –4 mA IOH = –8 mA IOH = –16 mA IOH = –24 mA IOH = –32 mA IOL = 100 mA IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA A or B inputs VI = 5.5 V or GND VI or VO = 5.5 V VI = 5.5 V or GND One input at VCC – 0.6 V, VI = VCC or GND VOH VOL II Ioff ICC ΔICC Ci VCC 1.65 V 2.3 V MIN 1.65 V to 5.5 V VCC – 0.1 1.2 1.9 2.4 2.3 3.8 4.5 V 3 V 1.65 V to 5.5 V 1.65 V 2.3 V 3 V 4.5 V 0 to 5.5 V 0 IO = 0 Other inputs at VCC or GND 1.65 V to 5.5 V 3 V to 5.5 V 3.3 V 4 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 V V mA mA mA mA pF UNIT ns UNIT ns (1) All typical values are at VCC = 3.3 V, TA = 25°C. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) Y VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V ± 0.2 V ± 0.15 V MIN MAX MIN MAX MIN MAX MIN MAX 3.4 2.2 ± 0.3 V 7.2 0.9 4.4 0.8 3.8 0.8 VCC = 5 V ± 0.5 V SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) VCC = 5 V ± 0.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TO PARAMETER FROM (INPUT) (OUTPUT) ± 0.2 V ± 0.15 V MIN MAX MIN MAX MIN MAX MIN MAX 4 3.1 ± 0.3 V 1.3 5.5 4.7 9 1 1 tpd A or B Y OPERATING CHARACTERISTICS TA = 25°C PARAMETER TEST CONDITIONS Cpd Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP 22 TYP 22 TYP 23 TYP 25 UNIT pF 4 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G00
    www.ti.com SCES212V –APRIL 1999–REVISED FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION SN74LVC1G00 Figure 1. Load Circuit and Voltage Waveforms Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN74LVC1G00 thtsuFrom OutputUnder TestC(see NoteA)LLOAD CIRCUITS1VLOADOpenGNDRLData InputTiming Input0 V0 V0 VtWInput0 VInputOutputWaveform 1S1 at V(see Note B)LOADOutputWaveform 2S1 at GND(see Note B)VOLVOH0 V»0 VOutputOutputt/tPLHPHLOpenTESTS1OutputControlVMVMVMVMVM1.8 V0.15 V±2.5 V0.2 V±3.3 V0.3 V±5 V0.5 V±1 MW1 MW1 MW1 MWVCCRL2 ×VCC2 ×VCC6 V2 ×VCCVLOADCL15 pF15 pF15 pF15 pF0.15 V0.15 V0.3 V0.3 VVD3 VVIVCC/2VCC/21.5 VVCC/2VM£2 ns£2 ns£2.5 ns£2.5 nsINPUTSRLt/trfVCCVCCVCCVLOADt/tPLZPZLGNDt/tPHZPZHVOLTAGE WAVEFORMSENABLEAND DISABLE TIMESLOW-AND HIGH-LEVELENABLINGVOLTAGE WAVEFORMSPROPAGATION DELAYTIMESINVERTINGAND NONINVERTING OUTPUTSNOTES:A.Cincludes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR10 MHz, Z= 50.D.The outputs are measured one at a time, with one transition per measurement.E.tand tare the same as t.F.tand tare the same as t.G.tand tare the same as t.H.All parameters and waveforms are not applicable to all devices.LOPLZPHZdisPZLPZHenPLHPHLpd£WVOLTAGE WAVEFORMSPULSE DURATIONVOLTAGE WAVEFORMSSETUPAND HOLD TIMESVIVIVIVMVMV/2LOADtPZLtPLZtPHZtPZHV–VOHDV+ VOLDVMVMVMVMVOLVOHVIVIVOHVOLVMVMVMVMtPLHtPHLtPLHtPHL
    SN74LVC1G00 SCES212V –APRIL 1999–REVISED FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 2. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G00 thtsuFrom OutputUnder TestC(see NoteA)LLOAD CIRCUITS1VLOADOpenGNDRLData InputTiming Input0 V0 V0 VtWInput0 VInputOutputWaveform 1S1 at V(see Note B)LOADOutputWaveform 2S1 at GND(see Note B)VOLVOH0 V»0 VOutputOutputTESTS1t/tPLHPHLOpenOutputControlVMVMVMVMVM1.8 V0.15 V±2.5 V0.2 V±3.3 V0.3 V±5 V0.5 V±1 kW500W500W500WVCCRL2 ×VCC2 ×VCC6 V2 ×VCCVLOADCL30 pF30 pF50 pF50 pF0.15 V0.15 V0.3 V0.3 VVD3 VVIVCC/2VCC/21.5 VVCC/2VM£2 ns£2 ns£2.5 ns£2.5 nsINPUTSRLt/trfVCCVCCVCCVLOADt/tPLZPZLGNDt/tPHZPZHVOLTAGE WAVEFORMSENABLEAND DISABLE TIMESLOW-AND HIGH-LEVELENABLINGVOLTAGE WAVEFORMSPROPAGATION DELAYTIMESINVERTINGAND NONINVERTING OUTPUTSNOTES:A.Cincludes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR10 MHz, Z= 50.D.The outputs are measured one at a time, with one transition per measurement.E.tand tare the same as t.F.tand tare the same as t.G.tand tare the same as t.H.All parameters and waveforms are not applicable to all devices.LOPLZPHZdisPZLPZHenPLHPHLpd£WVOLTAGE WAVEFORMSPULSE DURATIONVOLTAGE WAVEFORMSSETUPAND HOLD TIMESVIVIVIVMVMV/2LOADtPZLtPLZtPHZtPZHV–VOHDV+ VOLDVMVMVMVMVOLVOHVIVIVOHVOLVMVMVMVMtPLHtPHLtPLHtPHL
    www.ti.com 4-Feb-2010 PACKAGE OPTION ADDENDUM PACKAGING INFORMATION Orderable Device Status (1) SN74LVC1G00DBVR ACTIVE Package Type SOT-23 Package Drawing DBV SN74LVC1G00DBVRE4 ACTIVE SOT-23 DBV SN74LVC1G00DBVRG4 ACTIVE SOT-23 DBV SN74LVC1G00DBVT ACTIVE SOT-23 DBV SN74LVC1G00DBVTE4 ACTIVE SOT-23 DBV SN74LVC1G00DBVTG4 ACTIVE SOT-23 DBV SN74LVC1G00DCKR ACTIVE SC70 SN74LVC1G00DCKRE4 ACTIVE SC70 SN74LVC1G00DCKRG4 ACTIVE SC70 SN74LVC1G00DCKT ACTIVE SC70 SN74LVC1G00DCKTE4 ACTIVE SC70 SN74LVC1G00DCKTG4 ACTIVE SC70 SN74LVC1G00DRLR ACTIVE SN74LVC1G00DRLRG4 ACTIVE SOT SOT DCK DCK DCK DCK DCK DCK DRL DRL SN74LVC1G00YZPR ACTIVE DSBGA YZP Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Qty 3000 Green (RoHS & 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) 3000 Green (RoHS & SNAGCU Level-1-260C-UNLIM no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1
    www.ti.com 4-Feb-2010 PACKAGE OPTION ADDENDUM Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G00 : • Enhanced Product: SN74LVC1G00-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2
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