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STM32F103RC_Datasheet.pdf
Table 1. Device summary
1 Introduction
2 Description
2.1 Device overview
Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts
Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram
Figure 2. Clock tree
2.2 Full compatibility throughout the family
Table 3. STM32F103xx family
2.3 Overview
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM
2.3.2 Embedded Flash memory
2.3.3 CRC (cyclic redundancy check) calculation unit
2.3.4 Embedded SRAM
2.3.5 FSMC (flexible static memory controller)
2.3.6 LCD parallel interface
2.3.7 Nested vectored interrupt controller (NVIC)
2.3.8 External interrupt/event controller (EXTI)
2.3.9 Clocks and startup
2.3.10 Boot modes
2.3.11 Power supply schemes
2.3.12 Power supply supervisor
2.3.13 Voltage regulator
2.3.14 Low-power modes
2.3.15 DMA
2.3.16 RTC (real-time clock) and backup registers
2.3.17 Timers and watchdogs
Table 4. High-density timer feature comparison
2.3.18 I²C bus
2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)
2.3.20 Serial peripheral interface (SPI)
2.3.21 Inter-integrated sound (I2S)
2.3.22 SDIO
2.3.23 Controller area network (CAN)
2.3.24 Universal serial bus (USB)
2.3.25 GPIOs (general-purpose inputs/outputs)
2.3.26 ADC (analog to digital converter)
2.3.27 DAC (digital-to-analog converter)
2.3.28 Temperature sensor
2.3.29 Serial wire JTAG debug port (SWJ-DP)
2.3.30 Embedded Trace Macrocell™
3 Pinouts and pin descriptions
Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout
Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout
Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout
Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout
Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout
Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side
Table 5. High-density STM32F103xx pin definitions
Table 6. FSMC pin definition
4 Memory mapping
Figure 9. Memory map
5 Electrical characteristics
5.1 Parameter conditions
5.1.1 Minimum and maximum values
5.1.2 Typical values
5.1.3 Typical curves
5.1.4 Loading capacitor
5.1.5 Pin input voltage
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
5.1.6 Power supply scheme
Figure 12. Power supply scheme
5.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
5.2 Absolute maximum ratings
Table 7. Voltage characteristics
Table 8. Current characteristics
Table 9. Thermal characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 10. General operating conditions
5.3.2 Operating conditions at power-up / power-down
Table 11. Operating conditions at power-up / power-down
5.3.3 Embedded reset and power control block characteristics
Table 12. Embedded reset and power control block characteristics
5.3.4 Embedded reference voltage
Table 13. Embedded internal reference voltage
5.3.5 Supply current characteristics
Table 14. Maximum current consumption in Run mode, code with data processing running from Flash
Table 15. Maximum current consumption in Run mode, code with data processing running from RAM
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values
Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values
Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values
Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values
Table 18. Typical current consumption in Run mode, code with data processing running from Flash
Table 19. Typical current consumption in Sleep mode, coderunning from Flash or RAM
Table 20. Peripheral current consumption
5.3.6 External clock source characteristics
Table 21. High-speed external user clock characteristics
Table 22. Low-speed external user clock characteristics
Figure 20. High-speed external clock source AC timing diagram
Figure 21. Low-speed external clock source AC timing diagram
Table 23. HSE 4-16 MHz oscillator characteristics
Figure 22. Typical application with an 8 MHz crystal
Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)
Figure 23. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
Table 25. HSI oscillator characteristics
Table 26. LSI oscillator characteristics
Table 27. Low-power mode wakeup timings
5.3.8 PLL characteristics
Table 28. PLL characteristics
5.3.9 Memory characteristics
Table 29. Flash memory characteristics
Table 30. Flash memory endurance and data retention
5.3.10 FSMC characteristics
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 34. Asynchronous multiplexed PSRAM/NOR write timings
Figure 28. Synchronous multiplexed NOR/PSRAM read timings
Table 35. Synchronous multiplexed NOR/PSRAM read timings
Figure 29. Synchronous multiplexed PSRAM write timings
Table 36. Synchronous multiplexed PSRAM write timings
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Figure 31. Synchronous non-multiplexed PSRAM write timings
Table 38. Synchronous non-multiplexed PSRAM write timings
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access
Table 39. Switching characteristics for PC Card/CF read and write cycles
Figure 38. NAND controller waveforms for read access
Figure 39. NAND controller waveforms for write access
Figure 40. NAND controller waveforms for common memory read access
Figure 41. NAND controller waveforms for common memory write access
Table 40. Switching characteristics for NAND Flash read and write cycles
5.3.11 EMC characteristics
Table 41. EMS characteristics
Table 42. EMI characteristics
5.3.12 Absolute maximum ratings (electrical sensitivity)
Table 43. ESD absolute maximum ratings
Table 44. Electrical sensitivities
5.3.13 I/O port characteristics
Table 45. I/O static characteristics
Table 46. Output voltage characteristics
Table 47. I/O AC characteristics
Figure 42. I/O AC characteristics definition
5.3.14 NRST pin characteristics
Table 48. NRST pin characteristics
Figure 43. Recommended NRST pin protection
5.3.15 TIM timer characteristics
Table 49. TIMx characteristics
5.3.16 Communications interfaces
Table 50. I2C characteristics
Figure 44. I2C bus AC waveforms and measurement circuit
Table 51. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)
Table 52. SPI characteristics
Figure 45. SPI timing diagram - slave mode and CPHA = 0
Figure 46. SPI timing diagram - slave mode and CPHA = 1(1)
Figure 47. SPI timing diagram - master mode(1)
Table 53. I2S characteristics
Figure 48. I2S slave timing diagram (Philips protocol)(1)
Figure 49. I2S master timing diagram (Philips protocol)(1)
Figure 50. SDIO high-speed mode
Figure 51. SD default mode
Table 54. SD / MMC characteristics
Table 55. USB startup time
Table 56. USB DC electrical characteristics
Figure 52. USB timings: definition of data signal rise and fall time
Table 57. USB: full-speed electrical characteristics
5.3.17 CAN (controller area network) interface
5.3.18 12-bit ADC characteristics
Table 58. ADC characteristics
Table 59. RAIN max for fADC = 14 MHz
Table 60. ADC accuracy - limited test conditions
Table 61. ADC accuracy
Figure 53. ADC accuracy characteristics
Figure 54. Typical connection diagram using the ADC
Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 56. Power supply and reference decoupling (VREF+ connected to VDDA)
5.3.19 DAC electrical specifications
Table 62. DAC characteristics
Figure 57. 12-bit buffered /non-buffered DAC
5.3.20 Temperature sensor characteristics
Table 63. TS characteristics
6 Package characteristics
6.1 Package mechanical data
Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline
Table 64. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data
Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline
Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data
Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline
Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data
Figure 62. Recommended PCB design rules (0.5 mm pitch BGA)
Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
Figure 64. Recommended footprint(1)
Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
Figure 66. Recommended footprint(1)
Table 68. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Figure 67. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
Figure 68. Recommended footprint(1)
Table 69. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
6.2 Thermal characteristics
Table 70. Package thermal characteristics
6.2.1 Reference document
6.2.2 Selecting the product temperature range
Figure 69. LQFP100 PD max vs. TA
7 Part numbering
Table 71. Ordering information scheme
8 Revision history
STM32F103xC STM32F103xD
STM32F103xE
High-density performance line ARM-based 32-bit MCU with 256 to
512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■ Memories
– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
■ Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■ 3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
■ 2 × 12-bit D/A converters
■ DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I2Ss, SPIs, I2Cs and USARTs
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
FBGA
WLCSP64
LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm
■ Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■ Up to 11 timers
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
■ Up to 13 communication interfaces
– Up to 2 × I2C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I2S
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
■ CRC calculation unit, 96-bit unique ID
■ ECOPACK® packages
Table 1.
Device summary
Reference
Part number
STM32F103xC
STM32F103xD
STM32F103RC STM32F103VC
STM32F103ZC
STM32F103RD STM32F103VD
STM32F103ZD
STM32F103xE
STM32F103RE STM32F103ZE
STM32F103VE
September 2009
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www.st.com
1
Contents
Contents
STM32F103xC, STM32F103xD, STM32F103xE
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2
2.3.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5
2.3.6
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
2.3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.10
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11
2.3.12
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
2.3.14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
2.3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.18
Universal synchronous/asynchronous receiver transmitters (USARTs) 21
2.3.19
2.3.20
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.21
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.22
2.3.23
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.24
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26
ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.27
2.3.28
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3
4
5
2.3.29
2.3.30
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2
5.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.1
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.2
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.4
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.5
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.1
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
5.3.2
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 43
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.4
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.6
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.7
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.9
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.10
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 81
5.3.12
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.13
5.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.15
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.16
5.3.17
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 97
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.18
5.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Contents
STM32F103xC, STM32F103xD, STM32F103xE
5.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.1
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2
6.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115
6.2.2
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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List of tables
List of tables
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1.
STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11
Table 2.
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.
High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.
High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6.
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7.
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8.
Table 9.
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12.
Table 13.
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Maximum current consumption in Run mode, code with data processing
Table 19.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48
Table 17.
Typical current consumption in Run mode, code with data processing
Table 18.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical current consumption in Sleep mode, coderunning from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 62
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 63
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 76
Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 79
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
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List of tables
STM32F103xC, STM32F103xD, STM32F103xE
Table 45.
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 47.
Table 48.
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 49.
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 50.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 51.
Table 52.
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 53.
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 54.
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 55.
Table 56.
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 57.
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 58.
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 59.
Table 60.
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 61.
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 62.
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 63.
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
Table 64.
0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 65.
Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 67.
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111
Table 68.
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112
Table 69.
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113
Table 70.
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 71. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6/123
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STM32F103xC, STM32F103xD, STM32F103xE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24
STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25
STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26
STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27
STM32F103xC and STM32F103xE performance line
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F103xC and STM32F103xE performance line
WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9.
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
Figure 8.
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46
Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19. Typical current consumption in Standby mode versus temperature at
different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21.
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 73
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76
Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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STM32F103xC, STM32F103xD, STM32F103xE
Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 78
Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 79
Figure 42.
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 43. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 44.
Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 46. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 47. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 48.
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 49.
Figure 50. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 51. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 52. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 53. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 54. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 101
Figure 56. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102
Figure 57.
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 106
Figure 59.
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 60.
Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 63.
LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 64. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 65.
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112
Figure 66. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 67.
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113
Figure 68. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 69.
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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