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W25Q128(芯片资料).pdf
W25Q128BV
3V 128M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: April 01, 2011
- 1 - Revision E
W25Q128BV
Table of Contents
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ............................................................................................................... 5
FEATURES ....................................................................................................................................... 5
PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6
Pad Configuration WSON 8x6-mm ...................................................................................... 6
3.1
Pad Description WSON 8x6-mm .......................................................................................... 6
3.2
3.3
Pin Configuration SOIC 300-mil ........................................................................................... 7
Pin Description SOIC 300-mil ............................................................................................... 7
3.4
3.5
Ball Configuration TFBGA 8x6-mm ...................................................................................... 8
3.6
Ball Description TFBGA 8x6-mm ......................................................................................... 8
PIN DESCRIPTIONS ........................................................................................................................ 9
4.1
Chip Select (/CS) .................................................................................................................. 9
4.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9
4.3 Write Protect (/WP) .............................................................................................................. 9
4.4
HOLD (/HOLD) ..................................................................................................................... 9
4.5
Serial Clock (CLK) ................................................................................................................ 9
BLOCK DIAGRAM .......................................................................................................................... 10
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1
SPI OPERATIONS ............................................................................................................. 11
6.1.1 Standard SPI Instructions ..................................................................................................... 11
6.1.2 Dual SPI Instructions ............................................................................................................ 11
6.1.3 Quad SPI Instructions ........................................................................................................... 11
6.1.4 Hold Function ....................................................................................................................... 11
6.2 WRITE PROTECTION ....................................................................................................... 12
6.2.1 Write Protect Features ......................................................................................................... 12
STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 13
STATUS REGISTERS ........................................................................................................ 13
7.1
7.1.1 BUSY Status (BUSY) ............................................................................................................ 13
7.1.2 Write Enable Latch Status (WEL) ........................................................................................ 13
7.1.3 Block Protect Bits (BP2, BP1, BP0) ...................................................................................... 13
7.1.4 Top/Bottom Block Protect Bit (TB) ........................................................................................ 13
7.1.5 Sector/Block Protect Bit (SEC) ............................................................................................. 13
7.1.6 Complement Protect Bit (CMP) ............................................................................................ 14
7.1.7 Status Register Protect Bits (SRP1, SRP0) .......................................................................... 14
7.1.8 Erase/Program Suspend Status (SUS) ................................................................................ 14
7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 14
7.1.10 Quad Enable Bit (QE) ......................................................................................................... 15
7.1.11 Status Register Memory Protection (CMP = 0) ................................................................... 16
- 2 -
W25Q128BV
7.2
7.1.12 Status Register Memory Protection (CMP = 1) ................................................................... 17
INSTRUCTIONS ................................................................................................................. 18
7.2.1 Manufacturer and Device Identification ................................................................................ 18
Instruction Set Table 1 (Erase, Program Instructions) .......................................................... 19
7.2.2
7.2.3
Instruction Set Table 2 (Read Instructions) .......................................................................... 20
7.2.4
Instruction Set Table 3 (ID, Security Instructions) ................................................................ 21
7.2.5 Write Enable (06h) ............................................................................................................... 22
7.2.6 Write Enable for Volatile Status Register (50h) .................................................................... 22
7.2.7 Write Disable (04h) ............................................................................................................... 23
7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) ........................................ 24
7.2.9 Write Status Register (01h) .................................................................................................. 24
7.2.10 Read Data (03h) ................................................................................................................. 26
7.2.11 Fast Read (0Bh) ................................................................................................................. 27
7.2.12 Fast Read Dual Output (3Bh) ............................................................................................. 28
7.2.13 Fast Read Quad Output (6Bh) ............................................................................................ 29
7.2.14 Fast Read Dual I/O (BBh) ................................................................................................... 30
7.2.15 Fast Read Quad I/O (EBh) ................................................................................................. 32
7.2.16 Word Read Quad I/O (E7h) ................................................................................................ 34
7.2.17 Octal Word Read Quad I/O (E3h) ....................................................................................... 36
7.2.18 Set Burst with Wrap (77h) .................................................................................................. 38
7.2.19 Continuous Read Mode Bits (M7-0) ................................................................................... 39
7.2.20 Continuous Read Mode Reset (FFh or FFFFh) .................................................................. 39
7.2.21 Page Program (02h) ........................................................................................................... 40
7.2.22 Quad Input Page Program (32h) ........................................................................................ 41
7.2.23 Sector Erase (20h) ............................................................................................................. 42
7.2.24 32KB Block Erase (52h) ..................................................................................................... 43
7.2.25 64KB Block Erase (D8h) ..................................................................................................... 44
7.2.26 Chip Erase (C7h / 60h) ....................................................................................................... 45
7.2.27 Erase / Program Suspend (75h) ......................................................................................... 46
7.2.28 Erase / Program Resume (7Ah) ......................................................................................... 47
7.2.29 Power-down (B9h) .............................................................................................................. 48
7.2.30 Release Power-down / Device ID (ABh) ............................................................................. 49
7.2.31 Read Manufacturer / Device ID (90h) ................................................................................. 51
7.2.32 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 52
7.2.33 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 53
7.2.34 Read Unique ID Number (4Bh)........................................................................................... 54
7.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 55
7.2.36 Read SFDP Register (5Ah) ................................................................................................ 56
7.2.37 Erase Security Registers (44h) ........................................................................................... 59
7.2.38 Program Security Registers (42h) ...................................................................................... 60
7.2.39 Read Security Registers (48h) ........................................................................................... 61
Publication Release Date: April 01, 2011
- 3 - Revision E
W25Q128BV
ELECTRICAL CHARACTERISTICS ............................................................................................... 62
Absolute Maximum Ratings ................................................................................................ 62
8.1
Operating Ranges............................................................................................................... 62
8.2
8.3
Power-up Timing and Write Inhibit Threshold .................................................................... 63
DC Electrical Characteristics .............................................................................................. 64
8.4
AC Measurement Conditions .............................................................................................. 65
8.5
AC Electrical Characteristics .............................................................................................. 66
8.6
8.7
AC Electrical Characteristics (cont’d) ................................................................................. 67
Serial Output Timing ........................................................................................................... 68
8.8
8.9
Serial Input Timing .............................................................................................................. 68
8.10 HOLD Timing ...................................................................................................................... 68
8.11 WP Timing .......................................................................................................................... 68
PACKAGE SPECIFICATION .......................................................................................................... 69
9.1
8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 69
16-Pin SOIC 300-mil (Package Code F) ............................................................................ 70
9.2
9.3
24-Ball TFBGA 8x6-mm (Package Code C) ....................................................................... 71
ORDERING INFORMATION .......................................................................................................... 72
10.1 Valid Part Numbers and Top Side Marking ........................................................................ 73
REVISION HISTORY ...................................................................................................................... 74
8.
9.
10.
11.
- 4 -
W25Q128BV
1. GENERAL DESCRIPTION
The W25Q128BV (8M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current
consumption as low as 4mA active and 1µA for power-down.
The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV
has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See Figure 2.)
The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 280MHz (70MHz x 4) for Quad SPI
when using the Fast Read Quad SPI instructions. These transfer rates can out perform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer
and device identification with a 64-bit Unique Serial Number.
2. FEATURES
• Family of SpiFlash Memories
– W25Q128BV: 128M-bit/16M-byte
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash
– 104/70MHz Dual Output/Quad SPI clocks
– 208/280MHz equivalent Dual /Quad SPI
– 35MB/S continuous data transfer rate
– Up to 5X that of ordinary Serial Flash
– More than 100,000 erase/program cycles(1)
– More than 20-year data retention
• Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
• Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, <1µA Power-down current
– -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Program one to 256 bytes
– Erase/Program Suspend & Resume
• Advanced Security Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Lock-Down and OTP array protection
– 64-Bit Unique Serial Number for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
• Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 16-pin SOIC 300-mil
– 24-ball TFBGA 8x6-mm
– Contact Winbond for KGD and other options
Note 1: More than 100k Block Erase/Program cycles for Industrial and Automotive temperature; more than 10k full
chip Erase/Program cycles tested in compliance with AEC-Q100.
Publication Release Date: April 01, 2011
- 5 - Revision E
W25Q128BV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25Q128BV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package
code F) and a 24-ball 8x6-mm TFBGA (package code C) as shown in Figure 1a-c respectively. Package
diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
/CS
DO (IO1)
/WP (IO2)
GND
Top View
1
2
3
4
8
7
6
5
VCC
/HOL
D (IO3)
CLK
DI (IO
0)
Figure 1a. W25Q128BV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)
3.2 Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
1
2
3
4
5
6
7
8
/CS
DO (IO1)
/WP (IO2)
GND
DI (IO0)
CLK
/HOLD (IO3)
VCC
I/O
I
I/O
I/O
I/O
I
I/O
FUNCTION
Chip Select Input
Data Output (Data Input Output 1)*1
Write Protect Input ( Data Input Output 2)*2
Ground
Data Input (Data Input Output 0)*1
Serial Clock Input
Hold Input (Data Input Output 3)*2
Power Supply
*1: IO0 and IO1 are used for Standard and Dual SPI instructions
*2: IO0 – IO3 are used for Quad SPI instructions
- 6 -
3.3 Pin Configuration SOIC 300-mil
Top View
W25Q128BV
/HOLD (IO3)
VCC
NC
NC
NC
NC
/CS
DO (IO1)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
DI (IO0)
NC
NC
NC
NC
GND
/WP (IO2)
Figure 1b. W25Q128BV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.4 Pin Description SOIC 300-mil
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN NAME
/HOLD (IO3)
VCC
N/C
N/C
N/C
N/C
/CS
DO (IO1)
/WP (IO2)
GND
N/C
N/C
N/C
N/C
DI (IO0)
CLK
I/O
I/O
I
I/O
I/O
I/O
I
FUNCTION
Hold Input (Data Input Output 3)*2
Power Supply
No Connect
No Connect
No Connect
No Connect
Chip Select Input
Data Output (Data Input Output 1)*1
Write Protect Input (Data Input Output 2)*2
Ground
No Connect
No Connect
No Connect
No Connect
Data Input (Data Input Output 0)*1
Serial Clock Input
*1: IO0 and IO1 are used for Standard and Dual SPI instructions
*2: IO0 – IO3 are used for Quad SPI instructions
Publication Release Date: April 01, 2011
- 7 - Revision E
3.5 Ball Configuration TFBGA 8x6-mm
W25Q128BV
Top View
A1
NC
B1
NC
C1
NC
D1
NC
E1
NC
F1
NC
A2
NC
B2
CLK
C2
/CS
D2
A3
NC
B3
GND
C3
NC
D3
A4
NC
B4
VCC
C4
/WP (IO2)
D4
DO(IO1)
DI(IO0)
/HOLD(IO3)
E2
NC
F2
NC
E3
NC
F3
NC
E4
NC
F4
NC
Figure 1c. W25Q128BV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code C)
3.6 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
B2
B3
B4
C2
C4
D2
D3
D4
CLK
GND
VCC
/CS
/WP (IO2)
DO (IO1)
DI (IO0)
/HOLD (IO3)
Multiple
NC
I/O
I
I
I/O
I/O
I/O
I/O
FUNCTION
Serial Clock Input
Ground
Power Supply
Chip Select Input
Write Protect Input (Data Input Output 2)*2
Data Output (Data Input Output 1)*1
Data Input (Data Input Output 0)*1
Hold Input (Data Input Output 3)*2
No Connect
*1: IO0 and IO1 are used for Standard and Dual SPI instructions
*2: IO0 – IO3 are used for Quad SPI instructions
- 8 -
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