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LAN8720A(芯片资料).pdf
Chapter 1 Introduction
1.1 General Terms and Conventions
1.2 General Description
Figure 1.1 System Block Diagram
Figure 1.2 Architectural Overview
Chapter 2 Pin Description and Configuration
Figure 2.1 24-QFN Pin Assignments (TOP VIEW)
Table 2.1 RMII Signals
Table 2.2 LED Pins
Table 2.3 Serial Management Interface (SMI) Pins
Table 2.4 Ethernet Pins
Table 2.5 Miscellaneous Pins
Table 2.6 Analog Reference Pins
Table 2.7 Power Pins
2.1 Pin Assignments
Table 2.8 24-QFN Package Pin Assignments
2.2 Buffer Types
Table 2.9 Buffer Types
Chapter 3 Functional Description
3.1 Transceiver
3.1.1 100BASE-TX Transmit
Figure 3.1 100BASE-TX Transmit Data Path
Table 3.1 4B/5B Code Table
3.1.2 100BASE-TX Receive
Figure 3.2 100BASE-TX Receive Data Path
Figure 3.3 Relationship Between Received Data and Specific MII Signals
3.1.3 10BASE-T Transmit
3.1.4 10BASE-T Receive
3.2 Auto-negotiation
3.2.1 Parallel Detection
3.2.2 Restarting Auto-negotiation
3.2.3 Disabling Auto-negotiation
3.2.4 Half vs. Full Duplex
3.3 HP Auto-MDIX Support
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection
3.4 MAC Interface
3.4.1 RMII
3.5 Serial Management Interface (SMI)
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle
3.6 Interrupt Management
3.6.1 Primary Interrupt System
Table 3.2 Interrupt Management Table
3.6.2 Alternate Interrupt System
Table 3.3 Alternative Interrupt System Management Table
3.7 Configuration Straps
3.7.1 PHYAD[0]: PHY Address Configuration
3.7.2 MODE[2:0]: Mode Configuration
Table 3.4 MODE[2:0] Bus
Table 3.5 Pin Names for Mode Bits
3.7.3 REGOFF: Internal +1.2V Regulator Configuration
3.7.4 nINTSEL: nINT/REFCLKO Configuration
Table 3.6 nINTSEL Configuration
Figure 3.7 External 50MHz clock sources the REF_CLK
Figure 3.8 Sourcing REF_CLK from a 25MHz Crystal
Figure 3.9 Sourcing REF_CLK from External 25MHz Source
3.8 Miscellaneous Functions
3.8.1 LEDs
Figure 3.10 LED1/REGOFF Polarity Configuration
Figure 3.11 LED2/nINTSEL Polarity Configuration
3.8.2 Variable Voltage I/O
3.8.3 Power-Down Modes
3.8.4 Isolate Mode
3.8.5 Resets
3.8.6 Carrier Sense
3.8.7 Link Integrity Test
3.8.8 Loopback Operation
Figure 3.12 Near-end Loopback Block Diagram
Figure 3.13 Far Loopback Block Diagram
Figure 3.14 Connector Loopback Block Diagram
3.9 Application Diagrams
3.9.1 Simplified System Level Application Diagram
Figure 3.15 Simplified System Level Application Diagram
3.9.2 Power Supply Diagram (1.2V Supplied by Internal Regulator)
Figure 3.16 Power Supply Diagram (1.2V Supplied by Internal Regulator)
3.9.3 Power Supply Diagram (1.2V Supplied by External Source)
Figure 3.17 Power Supply Diagram (1.2V Supplied by External Source)
3.9.4 Twisted-Pair Interface Diagram (Single Power Supply)
Figure 3.18 Twisted-Pair Interface Diagram (Single Power Supply)
3.9.5 Twisted-Pair Interface Diagram (Dual Power Supplies)
Figure 3.19 Twisted-Pair Interface Diagram (Dual Power Supplies)
Chapter 4 Register Descriptions
4.1 Register Nomenclature
Table 4.1 Register Bit Types
4.2 Control and Status Registers
Table 4.2 SMI Register Map
4.2.1 Basic Control Register
4.2.2 Basic Status Register
4.2.3 PHY Identifier 1 Register
4.2.4 PHY Identifier 2 Register
4.2.5 Auto Negotiation Advertisement Register
4.2.6 Auto Negotiation Link Partner Ability Register
4.2.7 Auto Negotiation Expansion Register
4.2.8 Mode Control/Status Register
4.2.9 Special Modes Register
4.2.10 Symbol Error Counter Register
4.2.11 Special Control/Status Indications Register
4.2.12 Interrupt Source Flag Register
4.2.13 Interrupt Mask Register
4.2.14 PHY Special Control/Status Register
Chapter 5 Operational Characteristics
5.1 Absolute Maximum Ratings*
5.2 Operating Conditions**
5.3 Power Consumption
5.3.1 REF_CLK In Mode
Table 5.1 Device Only Current Consumption and Power Dissipation (REF_CLK In Mode)
5.3.2 REF_CLK Out Mode
Table 5.2 Device Only Current Consumption and Power Dissipation (REF_CLK Out Mode)
5.4 DC Specifications
Table 5.3 Non-Variable I/O Buffer Characteristics
Table 5.4 Variable I/O Buffer Characteristics
Table 5.5 100BASE-TX Transceiver Characteristics
Table 5.6 10BASE-T Transceiver Characteristics
5.5 AC Specifications
5.5.1 Equivalent Test Load
Figure 5.1 Output Equivalent Test Load
5.5.2 Power Sequence Timing
Figure 5.2 Power Sequence Timing
Table 5.7 Power Sequence Timing Values
5.5.3 Power-On nRST & Configuration Strap Timing
Figure 5.3 Power-On nRST & Configuration Strap Timing
Table 5.8 Power-On nRST & Configuration Strap Timing Values
5.5.4 RMII Interface Timing
Figure 5.4 RMII Timing (REF_CLK Out Mode)
Table 5.9 RMII Timing Values (REF_CLK Out Mode)
Figure 5.5 RMII Timing (REF_CLK In Mode)
Table 5.10 RMII Timing Values (REF_CLK In Mode)
Table 5.11 RMII CLKIN (REF_CLK) Timing Values
5.5.5 SMI Timing
Figure 5.6 SMI Timing
Table 5.12 SMI Timing Values
5.6 Clock Circuit
Table 5.13 Crystal Specifications
Chapter 6 Package Outline
Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
LAN8720A/LAN8720Ai
Small Footprint RMII 10/100 Ethernet
Transceiver with HP Auto-MDIX Support
PRODUCT FEATURES
Highlights
Single-Chip Ethernet Physical Layer Transceiver
(PHY)
Comprehensive flexPWR® Technology
— Flexible Power Management Architecture
— LVCMOS Variable I/O voltage range: +1.6V to +3.6V
— Integrated 1.2V regulator
HP Auto-MDIX support
Miniature 24-pin QFN lead-free RoHS compliant
package (4 x 4 x 0.85mm height).
Target Applications
Set-Top Boxes
Networked Printers and Servers
Test Instrumentation
LAN on Motherboard
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems/Routers
DSL Modems/Routers
Digital Video Recorders
IP and Video Phones
Wireless Access Points
Digital Televisions
Digital Media Adaptors/Servers
Gaming Consoles
POE Applications (Refer to SMSC Application Note 17.18)
Datasheet
Key Benefits
High-Performance 10/100 Ethernet Transceiver
— Compliant with IEEE802.3/802.3u (Fast Ethernet)
— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
— Loop-back modes
— Auto-negotiation
— Automatic polarity detection and correction
— Link status change wake-up detection
— Vendor specific register functions
— Supports the reduced pin count RMII interface
Power and I/Os
— Various low power modes
— Integrated power-on reset circuit
— Two status LED outputs
— Latch-Up Performance Exceeds 150mA per EIA/JESD
78, Class II
— May be used with a single 3.3V supply
Additional Features
— Ability to use a low cost 25Mhz crystal for reduced BOM
— 24-pin QFN (4x4 mm) Lead-Free RoHS Compliant
Packaging
package with RMII
Environmental
— Extended commercial temperature range
— Industrial temperature range version available
(0°C to +85°C)
(-40°C to +85°C)
SMSC LAN8720A/LAN8720Ai
DATASHEET
Revision 1.2 (11-10-10)
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Order Numbers:
LAN8720A-CP-TR for 24-pin, QFN lead-free RoHS compliant package (0 to +85°C temp)
LAN8720Ai-CP-TR for 24-pin, QFN lead-free RoHS compliant package (-40 to +85°C temp)
Reel size is 4,000
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2010 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.2 (11-10-10)
2
DATASHEET
SMSC LAN8720A/LAN8720Ai
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2
3.2
3.7
3.5
3.6
Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1
100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2
10BASE-T Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3
3.1.4
10BASE-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1
Restarting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.2
3.2.3
Disabling Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.4
Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3
HP Auto-MDIX Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.1
RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial Management Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Primary Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.1
3.6.2
Alternate Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PHYAD[0]: PHY Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.1
MODE[2:0]: Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.2
REGOFF: Internal +1.2V Regulator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.7.3
3.7.4
nINTSEL: nINT/REFCLKO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.8 Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8.1
Variable Voltage I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8.2
Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8.3
Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.4
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.5
Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.6
Link Integrity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.8.7
3.8.8
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.9.1
Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . 43
3.9.2
3.9.3
Power Supply Diagram (1.2V Supplied by External Source). . . . . . . . . . . . . . . . . . . . . . 44
Twisted-Pair Interface Diagram (Single Power Supply). . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.9.4
3.9.5
Twisted-Pair Interface Diagram (Dual Power Supplies) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.9
Chapter 4 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2
4.2.1
Basic Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMSC LAN8720A/LAN8720Ai
3
DATASHEET
Revision 1.2 (11-10-10)
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PHY Identifier 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PHY Identifier 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Auto Negotiation Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Auto Negotiation Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Auto Negotiation Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Mode Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Special Modes Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Symbol Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Special Control/Status Indications Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Source Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PHY Special Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 5 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1
Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2
5.3
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
REF_CLK In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.1
5.3.2
REF_CLK Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Equivalent Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5.1
Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.2
Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.3
5.5.4
RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5.5
SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4
5.5
5.6
Chapter 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 7 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision 1.2 (11-10-10)
4
DATASHEET
SMSC LAN8720A/LAN8720Ai
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 24-QFN Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 100BASE-TX Transmit Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3.2 100BASE-TX Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3.7 External 50MHz clock sources the REF_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 3.8 Sourcing REF_CLK from a 25MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 3.9 Sourcing REF_CLK from External 25MHz Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 3.10 LED1/REGOFF Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 3.11 LED2/nINTSEL Polarity Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3.12 Near-end Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.13 Far Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3.14 Connector Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3.15 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3.16 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.17 Power Supply Diagram (1.2V Supplied by External Source) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.18 Twisted-Pair Interface Diagram (Single Power Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.19 Twisted-Pair Interface Diagram (Dual Power Supplies). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 5.4 RMII Timing (REF_CLK Out Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 5.5 RMII Timing (REF_CLK In Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.6 SMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SMSC LAN8720A/LAN8720Ai
5
DATASHEET
Revision 1.2 (11-10-10)
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
List of Tables
Table 2.1 RMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2.3 Serial Management Interface (SMI) Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2.4 Ethernet Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2.5 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.6 Analog Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.7 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.8 24-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.9 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.2 Interrupt Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3.3 Alternative Interrupt System Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3.4 MODE[2:0] Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.5 Pin Names for Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.6 nINTSEL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4.1 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 4.2 SMI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5.1 Device Only Current Consumption and Power Dissipation (REF_CLK In Mode) . . . . . . . . . . 64
Table 5.2 Device Only Current Consumption and Power Dissipation (REF_CLK Out Mode) . . . . . . . . . 65
Table 5.3 Non-Variable I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 5.4 Variable I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 5.5 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 5.6 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5.7 Power Sequence Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.8 Power-On nRST & Configuration Strap Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 5.9 RMII Timing Values (REF_CLK Out Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5.10 RMII Timing Values (REF_CLK In Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 5.11 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5.12 SMI Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 5.13 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision 1.2 (11-10-10)
6
DATASHEET
SMSC LAN8720A/LAN8720Ai
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Chapter 1 Introduction
1.1
General Terms and Conventions
The following is list of the general terms used throughout this document:
BYTE
FIFO
MAC
RMIITM
N/A
X
RESERVED
SMI
1.2
8-bits
First In First Out buffer; often used for elasticity buffer
Media Access Controller
Reduced Media Independent InterfaceTM
Not Applicable
Indicates that a logic state is “don’t care” or undefined.
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not guaranteed when reading reserved bits. Unless otherwise noted, do
not read or write to reserved addresses.
Serial Management Interface
General Description
The LAN8720A/LAN8720Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver
with variable I/O voltage that is compliant with the IEEE 802.3-2005 standards.
The LAN8720A/LAN8720Ai supports communication with an Ethernet MAC via a standard RMII
interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10Mbps
(10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8720A/LAN8720Ai implements auto-
negotiation to automatically determine the best possible speed and duplex mode of operation. HP
Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
The LAN8720A/LAN8720Ai supports both IEEE 802.3-2005 compliant and vendor-specific register
functions. However, no register access is required for operation. The initial configuration may be
selected via the configuration pins as described in Section 3.7, "Configuration Straps," on page 31.
Register-selectable configuration options may be used to further define the functionality of the
transceiver.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be
configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The
linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for
lower system power dissipation.
The LAN8720A/LAN8720Ai is available in both extended commercial and industrial temperature range
versions. A typical system application is shown in Figure 1.1.
SMSC LAN8720A/LAN8720Ai
7
DATASHEET
Revision 1.2 (11-10-10)
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
10/100
Ethernet
MAC
RMII
Mode
LAN8720A/
LAN8720Ai
MDI
LED
Transformer
RJ45
Crystal or
Clock
Oscillator
Figure 1.1 System Block Diagram
Mode Control
Reset Control
Auto-
Negotiation
SMI
Management
Control
100M TX
Logic
100M
Transmitter
Transmitter
10M TX
Logic
10M
Transmitter
i
c
g
o
L
I
I
M
R
100M RX
Logic
10M RX
Logic
DSP System:
Clock
Data Recovery
Equalizer
Receiver
10M PLL
Analog-to-
Digital
100M PLL
Squeltch
& Filters
LAN8720A/LAN8720Ai
Figure 1.2 Architectural Overview
MODE[0:2]
nRST
RMIISEL
TXD[0:1]
TXEN
RXD[0:1]
RXER
CRS_DV
MDC
MDIO
HP Auto-MDIX
MDIX
Control
PLL
Interrupt
Generator
LEDs
Central Bias
TXP/TXN
RXP/RXN
XTAL1/CLKIN
XTAL2
nINT
LED1
LED2
RBIAS
PHY Address
Latches
PHYAD0
Revision 1.2 (11-10-10)
8
DATASHEET
SMSC LAN8720A/LAN8720Ai
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