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OV7670_英文(芯片资料).pdf

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    General Description
    Features
    Ordering Information
    Applications
    Key Specifications
    Figure 1 OV7670/OV7171 Pin Diagram (Top View)
    Functional Description
    Figure 2 Functional Block Diagram
    Image Sensor Array
    Figure 3 Image Sensor Array
    Timing Generator
    Analog Signal Processor
    A/D Converters
    Test Pattern Generator
    Digital Signal Processor (DSP)
    Image Scaler
    Digital Video Port
    SCCB Interface
    LED and Strobe Flash Control Output
    Pin Description
    Table 1 Pin Description
    Electrical Characteristics
    Table 2 Absolute Maximum Ratings
    Table 3 DC Characteristics (-30C < TA < 70C)
    Table 4 Functional and AC Characteristics (-30C < TA < 70C)
    Timing Specifications
    Figure 4 SCCB Timing Diagram
    Figure 5 Horizontal Timing
    Figure 6 VGA Frame Timing
    Figure 7 QVGA Frame Timing
    Figure 8 QQVGA Frame Timing
    Figure 9 CIF Frame Timing
    Figure 10 QCIF Frame Timing
    Figure 11 RGB 565 Output Timing Diagram
    Figure 12 RGB 555 Output Timing Diagram
    Figure 13 RGB 444 Output Timing Diagram
    Register Set
    Table 5 Device Control Register List
    Package Specifications
    Figure 14 OV7670/OV7171 Package Specifications
    Table 6 OV7670/OV7171 Package Dimensions
    Sensor Array Center
    Figure 15 OV7670/OV7171 Sensor Array Center
    IR Reflow Ramp Rate Requirements
    OV7670/OV7171 Lead-Free Packaged Devices
    Figure 16 IR Reflow Ramp Rate Requirements
    Table 7 Reflow Conditions
    Revision History
    Version 1.0
    Version 1.01
    Version 1.1
    Version 1.2
    Version 1.3
    Omni ision ® Advanced Information Preliminary Datasheet OV7670/OV7171 CMOS VGA (640x480) CAMERACHIPTM with OmniPixel ® Technology General Description The OV7670/OV7171 CAMERACHIPTM is a low voltage CMOS image sensor that provides the full functionality of a single-chip VGA camera and image processor in a small footprint package. The OV7670/OV7171 provides full-frame, sub-sampled or windowed 8-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. This product has an image array capable of operating at up to 30 frames per second (fps) in VGA with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision CAMERACHIPs use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise (FPN), smearing, blooming, etc., to produce a clean, fully stable color image. Pb Note: The OV7670/OV7171 uses a lead-free package. Features • • • • • • • • • • • • • • • • High sensitivity for low-light operation Low operating voltage for embedded portable apps Standard SCCB interface compatible with I2C interface Output support for Raw RGB, RGB (GRB 4:2:2, RGB565/555/444), YUV (4:2:2) and YCbCr (4:2:2) formats Supports image sizes: VGA, CIF, and any size scaling down from CIF to 40x30 VarioPixel® method for sub-sampling Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Band Filter (ABF), and Automatic Black-Level Calibration (ABLC) Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), and anti-blooming ISP includes noise reduction and defect correction Supports LED and flash strobe mode Supports scaling Lens shading correction Flicker (50/60 Hz) auto detection Saturation level auto adjust (UV adjust) Edge enhancement level auto adjust De-noise level auto adjust Ordering Information Product OV07670-VL2A (Color, lead-free) OV07171-VL2A (B&W, lead-free) Package 24 pin CSP2 24 pin CSP2 Applications • • • • Cellular and Picture Phones Toys PC Multimedia Digital Still Cameras Key Specifications Active Array Size 640 x 480 Power Supply Power Requirements Temperature Range Digital Core 1.8VDC +10% Analog 2.45V to 3.0V I/O 1.7V to 3.0Va Active 60 mW typical Standby < 20 µA Operation -30°C to 70°C Stable Image 0°C to 50°C (15fps VGA YUV format) Output Formats (8-bit) • YUV/YCbCr 4:2:2 • RGB565/555/444 • GRB 4:2:2 • Raw RGB Data Lens Size 1/6" Chief Ray Angle 25° Maximum Image Transfer Rate 30 fps for VGA Sensitivity 1.3 V/(Lux • sec) S/N Ratio 46 dB Dynamic Range 52 dB Scan Mode Progressive Electronics Exposure Up to 510:1 (for selected fps) Pixel Size 3.6 µm x 3.6 µm Dark Current 12 mV/s at 60°C Well Capacity 17 K e Image Area 2.36 mm x 1.76 mm Package Dimensions 3785 µm x 4235 µm a. I/O power should be 2.45V or higher when using the internal regulator for Core (1.8V); otherwise, it is necessary to provide an external 1.8V for the Core power supply. Figure 1 OV7670/OV7171 Pin Diagram (Top View) A1 A2 A3 AVDD SIO_D SIO_C B1 B2 B3 PWDN VREF2 AGND A4 D1 B4 D0 A5 D3 B5 D2 C1 C2 DVDD VREF1 D1 D2 VSYNC HREF OV7670/OV7171 E1 E2 E3 PCLK STROBE XCLK F1 F2 F3 DOVDD RESET# DOGND E4 D7 F4 D6 E5 D5 F5 D4 Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 1
    OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Functional Description Figure 2 shows the functional block diagram of the OV7670/OV7171 image sensor. The OV7670/OV7171 includes: • • • • • • • • • • Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode) Analog Signal Processor A/D Converters Test Pattern Generator Digital Signal Processor (DSP) Image Scaler Timing Generator Digital Video Port SCCB Interface LED and Strobe Flash Control Output Figure 2 Functional Block Diagram Buffer Buffer Analog Processing G R B Test Pattern Generator A/D DSP (Lens shading correction, de-noise, white/ black pixel correction, auto white balance, etc.) 50/60 Hz Auto Detect Image Scaler FIFO Video Port D[7:0] Column Sense Amp Exposure/Gain Detect t c e l e S w o R Image Array (656 x 488) Clock Video Timing Generator Exposure/Gain Control Registers SCCB Interface XCLK STROBE HREF PCLK VSYNC RESET# PWDN SIO_C SIO_D 2 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006
    Omni ision Functional Description Image Sensor Array Test Pattern Generator The OV7670/OV7171 sensor has an image array of 656 x 488 pixels for a total of 320,128 pixels, of which 640 x 480 pixels are active (307,200 pixels). Figure 3 shows a cross-section of the image sensor array. The Test Pattern Generator features the following: • • • 8-bar color bar pattern Fade-to-gray color bar pattern Shift "1" in output pin Figure 3 Image Sensor Array Microlens Digital Signal Processor (DSP) Glass Blue Green Red Timing Generator In general, the timing generator controls the following functions: • • • • • Array control and frame generation Internal timing signal generation and distribution Frame rate timing Automatic Exposure Control (AEC) External timing outputs (VSYNC, HREF/HSYNC, and PCLK) Analog Signal Processor This block performs all analog image functions including: • • Automatic Gain Control (AGC) Automatic White Balance (AWB) A/D Converters After the Analog Processing block, the bayer pattern Raw signal is fed to a 10-bit analog-to-digital (A/D) converter shared by G and BR channels. This A/D converter operates at speeds up to 12 MHz and is fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). In addition to the A/D conversion, this block also has the following functions: • • Optional U/V channel delay • Digital Black-Level Calibration (BLC) Additional A/D range controls In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application. • This block controls the interpolation from Raw data to RGB and some image quality control. • Edge enhancement (a two-dimensional high pass filter) Color space converter (can change Raw data to RGB or YUV/YCbCr) RGB matrix to eliminate color cross talk • Hue and saturation control • • White/black pixel correction • • • • De-noise Lens shading correction Programmable gamma control Transfer 10-bit data to 8-bit Image Scaler This block controls all output and data formatting required prior to sending the image out. This block scales YUV/RGB output from VGA to CIF and almost any size under CIF. Digital Video Port Register bits COM2[1:0] increase IOL/IOH drive current and can be adjusted as a function of the customer’s loading. SCCB Interface The Serial Camera Control Bus (SCCB) interface controls to OmniVision the CAMERACHIP operation. Refer Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port. LED and Strobe Flash Control Output The OV7670/OV7171 has a Strobe mode that allows it to work with an external flash and LED. Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 3
    Omni ision Pin Description Pin Description Table 1 Pin Description Pin Number Name Pin Type Function/Description A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 D1 D2 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 AVDD SIO_D SIO_C D1a D3 Power Analog power supply I/O Input Output Output SCCB serial interface data I/O SCCB serial interface clock input YUV/RGB video component output bit[1] YUV/RGB video component output bit[3] PWDN Input (0)b Power Down Mode Selection 0: Normal mode 1: Power down mode VREF2 AGND D0 D2 DVDD VREF1 VSYNC HREF PCLK STROBE XCLK D7 D5 DOVDD Reference Reference voltage - connect to ground using a 0.1 µF capacitor Power Output Output Power Analog ground YUV/RGB video component output bit[0] YUV/RGB video component output bit[2] Power supply (+1.8 VDC) for digital logic core Reference Reference voltage - connect to ground using a 0.1 µF capacitor Output Output Output Output Input Output Output Power Vertical sync output HREF output Pixel clock output LED/strobe control output System clock input YUV/RGB video component output bit[7] YUV/RGB video component output bit[5] Digital power supply for I/O (1.7V ~ 3.0V) Clears all registers and resets them to their default values. RESET# Input DOGND D6 D4 Power Output Output 0: Reset mode 1: Normal mode Digital ground YUV/RGB video component output bit[6] YUV/RGB video component output bit[4] a. b. D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB) Input (0) represents an internal pull-down resistor. Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 4
    OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Electrical Characteristics Table 2 Ambient Storage Temperature Absolute Maximum Ratings Supply Voltages (with respect to Ground) -40ºC to +95ºC VDD-A VDD-C VDD-IO 4.5 V 3 V 4.5 V All Input/Output Voltages (with respect to Ground) Lead-free Temperature, Surface-mount process -0.3V to VDD-IO+0.5V 245ºC NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table 3 DC Characteristics (-30°C < TA < 70°C) Symbol Parameter Condition DC supply voltage – Analog DC supply voltage – Digital Core DC supply voltage – I/O power Active (Operating) Current Standby Current VDD-A VDD-C VDD-IO IDDA IDDS-SCCB IDDS-PWDN Standby Current VIH VIL VOH VOL IOH IOL IL a. Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Output current HIGH Output current LOW Input/Output Leakage VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loading IDD-C = 10mA, IDD-A = 8mA, without loading VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby Standard Output Loading = 25pF, 1.2KΩ b. c. d. – – – See Note a See Note c Min 2.45 1.62 1.7 Typ 2.75 1.8 – 10 + 8b 1 10 Max 3.0 1.98 3.0V 20 CMOS 0.7 x VDD-IO CMOS 0.9 x VDD-IO See Note d GND to VDD-IO 8 15 0.3 x VDD-IO 0.1 x VDD-IO ± 1 Unit V V V mA mA µA V V V V mA mA µA 5 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006
    Omni ision Electrical Characteristics Table 4 Functional and AC Characteristics (-30°C < TA < 70°C) Symbol Parameter Min Typ Max Functional Characteristics A/D A/D AGC Differential Non-Linearity Integral Non-Linearity Range Red/Blue Adjustment Range + 1/2 + 1 30 12 Unit LSB LSB dB dB MHz ns % ms ms KHz μs ns ns μs ns ns μs ns ns ns ns ns ns ns ns ns 10 21 45 24 42 50 0 100 600 Clock Frequency 400 900 Clock Duty Cycle 48 100 55 1 300 Clock Low Period Clock High Period Input Clock Period Input Clock Frequency SIO_C low to Data Out valid Bus free time before new START Setting time after software/hardware reset Settling time for register change (10 frames required) Inputs (PWDN, CLK, RESET#) fCLK tCLK tCLK:DC tS:RESET tS:REG SCCB Timing (see Figure 4) fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10) tPDV tSU tHD tPHH tPHL START condition Setup time STOP condition Setup time START condition Hold time PCLK[↓] to Data-out Valid SCCB Rise/Fall times PCLK[↓] to HREF[↓] PCLK[↓] to HREF[↑] Data-out Hold time Data-in Setup time 1.3 600 100 1.3 600 600 D[7:0] Setup time Data-in Hold time 50 15 8 0 0 300 5 5 5 D[7:0] Hold time AC Conditions: • VDD: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V • Rise/Fall Times: I/O: 5ns, Maximum SCCB: 300ns, Maximum • Input Capacitance: 10pf • Output Loading: 25pF, 1.2KΩ to 2.5V • fCLK: 24MHz Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 6
    OV7670/OV7171 CMOS VGA (OmniPixel®) CAMERACHIP™ Omni ision Timing Specifications Figure 4 SCCB Timing Diagram tF tHIGH tR tLOW tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tAA tDH tBUF SIO_C SIO_D IN SIO_D OUT Figure 5 Horizontal Timing PCLK HREF tPHL tPCLK tSU tHD (Row Data) tPHL D[7:0] Last Byte First Byte Last Byte Figure 6 VGA Frame Timing 3 x tLINE 17 tLINE VSYNC HREF HSYNC tPDV 510 x tLINE 480 x tLINE tLINE = 784 tP 144 tP 10 tLINE 640 tP 80 tP 45 tP 19 tP D[7:0] Invalid Data Invalid Data P0 - P639 Row 0 Row 1 Row 2 Row 479 NOTE: For Raw data, tP = tPCLK For YUV/RGB, tP = 2 x tPCLK 7 Proprietary to OmniVision Technologies Version 1.3, April 5, 2006
    Timing Specifications Omni ision Figure 7 QVGA Frame Timing VGA HREF (see Figure 7, VGA Frame Timing) QVGA HREF Figure 8 QQVGA Frame Timing VGA HREF (see Figure 7, VGA Frame Timing) QQVGA HREF (1 from 4, 120 from 480) Figure 9 CIF Frame Timing VGA HREF (see Figure 7, VGA Frame Timing) CIF HREF (3 from 5) Figure 10 QCIF Frame Timing QVGA HREF (see Figure 7, QVGA Frame Timing) QCIF HREF (3 from 5) Version 1.3, April 5, 2006 Proprietary to OmniVision Technologies 8
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