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SSD1306-Revision 1.1 (Charge Pump).pdf
1 GENERAL DESCRIPTION
2 FEATURES
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 DIE PAD FLOOR PLAN
6 PIN ARRANGEMENT
6.1 SSD1306TR1 pin assignment
7 PIN DESCRIPTION
8 FUNCTIONAL BLOCK DESCRIPTIONS
8.1 MCU Interface selection
8.1.1 MCU Parallel 6800-series Interface
8.1.2 MCU Parallel 8080-series Interface
8.1.3 MCU Serial Interface (4-wire SPI)
8.1.4 MCU Serial Interface (3-wire SPI)
8.1.5 MCU I2C Interface
8.1.5.1 I2C-bus Write data
8.1.5.2 Write mode for I2C
8.2 Command Decoder
8.3 Oscillator Circuit and Display Time Generator
8.4 FR synchronization
8.5 Reset Circuit
8.6 Segment Drivers / Common Drivers
8.7 Graphic Display Data RAM (GDDRAM)
8.8 SEG/COM Driving block
8.9 Power ON and OFF sequence
9 COMMAND TABLE
9.1 Data Read / Write
10 COMMAND DESCRIPTIONS
10.1 Fundamental Command
10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh)
10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh)
10.1.3 Set Memory Addressing Mode (20h)
10.1.4 Set Column Address (21h)
10.1.5 Set Page Address (22h)
10.1.6 Set Display Start Line (40h~7Fh)
10.1.7 Set Contrast Control for BANK0 (81h)
10.1.8 Set Segment Re-map (A0h/A1h)
10.1.9 Entire Display ON (A4h/A5h)
10.1.10 Set Normal/Inverse Display (A6h/A7h)
10.1.11 Set Multiplex Ratio (A8h)
10.1.12 Set Display ON/OFF (AEh/AFh)
10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h)
10.1.14 Set COM Output Scan Direction (C0h/C8h)
10.1.15 Set Display Offset (D3h)
10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)
10.1.17 Set Pre-charge Period (D9h)
10.1.18 Set COM Pins Hardware Configuration (DAh)
10.1.19 Set VCOMH Deselect Level (DBh)
10.1.20 NOP (E3h)
10.1.21 Status register Read
10.2 Graphic Acceleration Command
10.2.1 Horizontal Scroll Setup (26h/27h)
10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)
10.2.3 Deactivate Scroll (2Eh)
10.2.4 Activate Scroll (2Fh)
10.2.5 Set Vertical Scroll Area(A3h)
11 MAXIMUM RATINGS
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 Application Example
15 PACKAGE INFORMATION
15.1 SSD1306TR1 Detail Dimension
15.2 SSD1306Z Die Tray Information
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1306
Advance Information
OLED/PLED Segment/Common Driver with Controller
128 x 64 Dot Matrix
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
http://www.solomon-systech.com
SSD1306
Copyright © 2008 Solomon Systech Limited
Rev 1.1
P 1/59
Apr 2008
CONTENTS
1 GENERAL DESCRIPTION .......................................................................................................6
2 FEATURES...................................................................................................................................6
3 ORDERING INFORMATION ...................................................................................................6
4 BLOCK DIAGRAM ....................................................................................................................7
5 DIE PAD FLOOR PLAN ............................................................................................................8
6 PIN ARRANGEMENT..............................................................................................................11
SSD1306TR1 PIN ASSIGNMENT.......................................................................................................................... 11
7 PIN DESCRIPTION ..................................................................................................................13
6.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
9.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8 FUNCTIONAL BLOCK DESCRIPTIONS.............................................................................15
8.1 MCU INTERFACE SELECTION.............................................................................................................................. 15
MCU Parallel 6800-series Interface.......................................................................................................... 15
MCU Parallel 8080-series Interface.......................................................................................................... 16
MCU Serial Interface (4-wire SPI)............................................................................................................ 17
MCU Serial Interface (3-wire SPI)............................................................................................................ 18
MCU I2C Interface..................................................................................................................................... 19
COMMAND DECODER ......................................................................................................................................... 22
OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR..................................................................................... 22
FR SYNCHRONIZATION ....................................................................................................................................... 23
RESET CIRCUIT................................................................................................................................................... 23
SEGMENT DRIVERS / COMMON DRIVERS............................................................................................................ 24
GRAPHIC DISPLAY DATA RAM (GDDRAM)..................................................................................................... 25
SEG/COM DRIVING BLOCK ............................................................................................................................... 26
POWER ON AND OFF SEQUENCE ........................................................................................................................ 27
9 COMMAND TABLE .................................................................................................................28
DATA READ / WRITE .......................................................................................................................................... 33
10 COMMAND DESCRIPTIONS .............................................................................................34
10.1 FUNDAMENTAL COMMAND ................................................................................................................................ 34
Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) ................................................. 34
10.1.1
Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) ................................................ 34
10.1.2
Set Memory Addressing Mode (20h).......................................................................................................... 34
10.1.3
Set Column Address (21h) ......................................................................................................................... 35
10.1.4
Set Page Address (22h).............................................................................................................................. 36
10.1.5
Set Display Start Line (40h~7Fh) .............................................................................................................. 36
10.1.6
Set Contrast Control for BANK0 (81h)...................................................................................................... 36
10.1.7
Set Segment Re-map (A0h/A1h) ................................................................................................................. 36
10.1.8
10.1.9 Entire Display ON (A4h/A5h).................................................................................................................. 37
Set Normal/Inverse Display (A6h/A7h).................................................................................................. 37
10.1.10
10.1.11
Set Multiplex Ratio (A8h)....................................................................................................................... 37
10.1.12
Set Display ON/OFF (AEh/AFh) ........................................................................................................... 37
Set Page Start Address for Page Addressing Mode (B0h~B7h)............................................................. 37
10.1.13
Set COM Output Scan Direction (C0h/C8h).......................................................................................... 37
10.1.14
10.1.15
Set Display Offset (D3h) ........................................................................................................................ 37
10.1.16
Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) ............................................................... 40
10.1.17
Set Pre-charge Period (D9h) ................................................................................................................. 40
Set COM Pins Hardware Configuration (DAh)..................................................................................... 40
10.1.18
10.1.19
Set VCOMH Deselect Level (DBh) ........................................................................................................... 43
Solomon Systech
Apr 2008 P 2/59
Rev 1.1 SSD1306
NOP (E3h) ............................................................................................................................................. 43
10.1.20
10.1.21
Status register Read ............................................................................................................................... 43
10.2 GRAPHIC ACCELERATION COMMAND................................................................................................................. 44
10.2.1 Horizontal Scroll Setup (26h/27h) ............................................................................................................. 44
10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)..................................................................... 45
10.2.3 Deactivate Scroll (2Eh).............................................................................................................................. 46
10.2.4 Activate Scroll (2Fh).................................................................................................................................. 46
10.2.5
Set Vertical Scroll Area(A3h) .................................................................................................................... 46
11 MAXIMUM RATINGS..........................................................................................................47
12 DC CHARACTERISTICS.....................................................................................................48
13 AC CHARACTERISTICS.....................................................................................................49
14 APPLICATION EXAMPLE..................................................................................................55
15
PACKAGE INFORMATION................................................................................................56
15.1 SSD1306TR1 DETAIL DIMENSION..................................................................................................................... 56
15.2 SSD1306Z DIE TRAY INFORMATION.................................................................................................................. 58
SSD1306
Rev 1.1
P 3/59
Apr 2008
Solomon Systech
TABLES
TABLE 5-1 : SSD1306Z BUMP DIE PAD COORDINATES...................................................................................................... 10
TABLE 6-1 : SSD1306TR1 PIN ASSIGNMENT TABLE.......................................................................................................... 12
TABLE 7-1 : MCU BUS INTERFACE PIN SELECTION............................................................................................................ 14
TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ...................................................... 15
TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE................................................................................................................. 15
TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE................................................................................................................. 17
TABLE 8-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE................................................................................................. 17
TABLE 8-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE................................................................................................. 18
TABLE 9-1: COMMAND TABLE ........................................................................................................................................... 28
TABLE 9-2 : READ COMMAND TABLE................................................................................................................................. 33
TABLE 9-3 : ADDRESS INCREMENT TABLE (AUTOMATIC) ................................................................................................... 33
TABLE 10-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH NO REMAP.......................................... 38
TABLE 10-2 :EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP ................................................ 39
TABLE 10-3 : COM PINS HARDWARE CONFIGURATION ..................................................................................................... 40
TABLE 11-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS)................................................................................ 47
TABLE 12-1 : DC CHARACTERISTICS.................................................................................................................................. 48
TABLE 13-1 : AC CHARACTERISTICS.................................................................................................................................. 49
TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 50
TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 51
TABLE 13-4 : 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 52
TABLE 13-5 : 3-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 53
TABLE 13-6 :I2C INTERFACE TIMING CHARACTERISTICS.................................................................................................... 54
Solomon Systech
Apr 2008 P 4/59
Rev 1.1 SSD1306
FIGURES
FIGURE 4-1 SSD1306 BLOCK DIAGRAM .............................................................................................................................. 7
FIGURE 5-1 : SSD1306Z DIE DRAWING ............................................................................................................................... 8
FIGURE 5-2 : SSD1306Z ALIGNMENT MARK DIMENSIONS .................................................................................................... 9
FIGURE 6-1 : SSD1306TR1 PIN ASSIGNMENT ................................................................................................................. 11
FIGURE 7-1 PIN DESCRIPTION............................................................................................................................................. 13
FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ....................................................................... 16
FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE......................................................... 16
FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE .......................................................... 16
FIGURE 8-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ......................................................... 17
FIGURE 8-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE............................................................................... 18
FIGURE 8-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE............................................................................... 18
FIGURE 8-7 : I2C-BUS DATA FORMAT .................................................................................................................................. 20
FIGURE 8-8 : DEFINITION OF THE START AND STOP CONDITION ......................................................................................... 21
FIGURE 8-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION ................................................................................... 21
FIGURE 8-10 : DEFINITION OF THE DATA TRANSFER CONDITION......................................................................................... 21
FIGURE 8-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR .............................................................................. 22
FIGURE 8-12 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES ....................................................................................... 24
FIGURE 8-13 : GDDRAM PAGES STRUCTURE OF SSD1306................................................................................................ 25
FIGURE 8-14 : ENLARGEMENT OF GDDRAM (NO ROW RE-MAPPING AND COLUMN-REMAPPING)...................................... 25
FIGURE 8-15 : IREF CURRENT SETTING BY RESISTOR VALUE ............................................................................................. 26
FIGURE 8-16 : THE POWER ON SEQUENCE.......................................................................................................................... 27
FIGURE 8-17 : THE POWER OFF SEQUENCE........................................................................................................................ 27
FIGURE 10-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE ..................................................................... 34
FIGURE 10-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO ROW AND COLUMN-
REMAPPING) ............................................................................................................................................................... 34
FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE ......................................................... 35
FIGURE 10-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE.............................................................. 35
FIGURE 10-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT .............................................................. 36
FIGURE 10-6 :TRANSITION BETWEEN DIFFERENT MODES.................................................................................................... 37
FIGURE 10-7 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 1 COLUMN................................................................. 44
FIGURE 10-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 1 COLUMN ................................................................... 44
FIGURE 10-9 : HORIZONTAL SCROLLING SETUP EXAMPLE................................................................................................... 44
FIGURE 10-10 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE.................................................. 45
FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS...................................................................... 50
FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS................................................................................ 51
FIGURE 13-3 : 4-WIRE SERIAL INTERFACE CHARACTERISTICS............................................................................................. 52
FIGURE 13-4 : 3-WIRE SERIAL INTERFACE CHARACTERISTICS............................................................................................. 53
FIGURE 13-5 : I2C INTERFACE TIMING CHARACTERISTICS.................................................................................................. 54
FIGURE 14-1 : APPLICATION EXAMPLE OF SSD1306Z ....................................................................................................... 55
FIGURE 15-1 SSD1306TR1 DETAIL DIMENSION ................................................................................................................ 56
FIGURE 15-2 : SSD1306Z DIE TRAY INFORMATION ............................................................................................................ 58
SSD1306
Rev 1.1
P 5/59
Apr 2008
Solomon Systech
1 GENERAL DESCRIPTION
SSD1306 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light emitting
diode dot-matrix graphic display system. It consists of 128 segments and 64commons. This IC is
designed for Common Cathode type OLED panel.
The SSD1306 embeds with contrast control, display RAM and oscillator, which reduces the number of
external components and power consumption. It has 256-step brightness control. Data/Commands are
sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface,
I2C interface or Serial Peripheral Interface. It is suitable for many compact portable applications, such as
mobile phone sub-display, MP3 player and calculator, etc.
2 FEATURES
• Resolution: 128 x 64 dot matrix panel
• Power supply
o VDD = 1.65V to 3.3V for IC logic
o VCC = 7V to 15V for Panel driving
• For matrix display
o OLED driving output voltage, 15V maximum
o Segment maximum source current: 100uA
o Common maximum sink current: 15mA
o 256 step contrast brightness current control
• Embedded 128 x 64 bit SRAM display buffer
• Pin selectable MCU Interfaces:
o 8-bit 6800/8080-series parallel interface
o 3 /4 wire Serial Peripheral Interface
o
I2C Interface
• Screen saving continuous scrolling function in both horizontal and vertical direction
• RAM write synchronization signal
• Programmable Frame Rate and Multiplexing Ratio
• Row Re-mapping and Column Re-mapping
• On-Chip Oscillator
• Chip layout for COG & COF
• Wide range of operating temperature: -40°C to 85°C
3 ORDERING INFORMATION
Ordering Part Number SEG COM Package Form Reference Remark
Table 3-1: Ordering Information
SSD1306Z
128
64
COG
8
SSD1306TR1
104
48
TAB
11, 56
o Min SEG pad pitch : 47um
o Min COM pad pitch : 40um
o Die thickness: 300 +/- 25um
o 35mm film, 4 sprocket hole, Folding TAB
o 8-bit 80 / 8-bit 68 / SPI / I2C interface
o SEG, COM lead pitch 0.1mm x 0.997
=0.0997mm
o Die thickness: 457 +/- 25um
Solomon Systech
Apr 2008 P 6/59
Rev 1.1 SSD1306
4 BLOCK DIAGRAM
Figure 4-1 SSD1306 Block Diagram
RES#
CS#
D/C#
E (RD#)
R/W#(WR#)
BS2
BS1
BS0
D7
D6
D5
D4
D3
D2
D1
D0
VDD
VCC
VSSVLSS
SSD1306
COM62
COM60
|
|
COM2
COM0
SEG0
SEG1
|
|
SEG126
SEG127
COM1
COM3
|
|
COM61
COM63
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Rev 1.1
P 7/59
Apr 2008
Solomon Systech
5 DIE PAD FLOOR PLAN
Figure 5-1 : SSD1306Z Die Drawing
Pad 1
S
S
D
1
3
0
6
Z
Die size
Die thickness
Min I/O pad pitch
Min SEG pad pitch
Min COM pad pitch
Bump height
6.76mm x 0.86mm
300 +/- 25um
60um
47um
40um
Nominal 15um
Bump size
Pad 1, 106, 124, 256
Pad 2-18, 89-105, 107-123, 257-273
Pad 19-88
Pad 125-255
Pad 274-281 (TR pads)
80um x 50um
25ium x 80um
40um x 89um
31um x 59um
30um x 50um
Size
75um x 75um
75um x 75um
-
R37.5um, inner 18um
Position
(-2973, 0)
(2973, 0)
Alignment
mark
+ shape
+ shape
Circle
(2466.665, 7.575)
SSL Logo
(-2862.35, 144.82)
(For details dimension please see p.9 )
Note
(1) Diagram showing the Gold bumps face up.
(2) Coordinates are referenced to center of the chip.
(3) Coordinate units and size of all alignment marks are in um.
(4) All alignment keys do not contain gold
Y
SSD1306
X
Pad 1,2,3,…->281
Gold Bumps face up
Solomon Systech
Apr 2008 P 8/59
Rev 1.1 SSD1306
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