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Features • Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) • Automotive Temperature Range –40°C to 125°C • Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 400 kHz Compatibility • Write Protect Pin for Hardware Data Protection • 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes • Partial Page Writes are Allowed • Self-timed Write Cycle (5 ms max) • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • 8-lead JEDEC SOIC and 8-lead TSSOP Packages Description The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions. Table 1. Pin Configurations Function Pin Name Address Inputs A0 − A2 SDA Serial Data Serial Clock Input SCL Write Protect WP NC No Connect 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Two-wire Automotive Temperature Serial EEPROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8) AT24C01A AT24C02(1) AT24C04 AT24C08A AT24C16A Note: 1. AT24C02 not recom- new for mended design. 5092C–SEEPR–2/07 1

Absolute Maximum Ratings Operating Temperature......................................−55°C to +125°C *NOTICE: Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect. 2 AT24C01A/02/04/08A/16A 5092C–SEEPR–2/07

AT24C01A/02/04/08A/16A The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects. The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects. WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write oper- ations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. Table 2. Write Protect WP Pin Status At VCC At GND Part of the Array Protected 24C01A 24C02 24C04 24C08A 24C16A Full (1K) Array Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array Normal Read/Write Operations Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing. AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. 5092C–SEEPR–2/07 3

Table 3. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Test Condition Units Table 4. DC Characteristics Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted) Symbol VCC1 ICC ICC ISB1 ISB2 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V Read at 100 kHz Write at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS 1. VIL min and VIH max are reference only and are not tested. V mA mA µA µA µA µA V V V V Max 5.5 1.0 3.0 4.0 18.0 3.0 3.0 Typ 0.4 2.0 1.6 8.0 0.10 0.05 VCC x 0.3 VCC + 0.5 0.4 0.2 Min 2.7 −0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA 4 AT24C01A/02/04/08A/16A 5092C–SEEPR–2/07

AT24C01A/02/04/08A/16A Table 5. AC Characteristics Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(2) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time(1) Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(2) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time(2) Inputs Fall Time(2) Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25°C, Page Mode AT24C01A/02/04/08A/16A Max Min 400 1.2 0.6 0.1 1.2 0.6 0.6 0 100 0.6 50 1M 50 0.9 300 300 5 Units kHz µs µs ns µs µs µs µs µs ns ns ns µs ns ms Write Cycles 1. This parameter is characterized and is not 100% tested (TA = 25°C). 2. This parameter is characterized. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter- nal device. Data on the SDA pin may change only during SCL low time periods (see to Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 5 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. 5092C–SEEPR–2/07 5

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. Bus Timing Figure 2. SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing Figure 3. SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 6 AT24C01A/02/04/08A/16A 5092C–SEEPR–2/07

AT24C01A/02/04/08A/16A Figure 4. Data Validity Figure 5. Start and Stop Definition SDA SCL START Figure 6. Output Acknowledge STOP 5092C–SEEPR–2/07 7

Device Addressing Write Operations The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 7 on page 9). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre- sponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the three bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read opera- tion is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state. BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10). PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ- ous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send- 8 AT24C01A/02/04/08A/16A 5092C–SEEPR–2/07

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