ARM Cotrex-M3权威指南(英文).pdf

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The Deﬁ nitive Guide to the ARM Cortex-M3

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The Deﬁ nitive Guide to the ARM Cortex-M3 Joseph Yiu AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of Elsevier

Newnes is an imprint of Elsevier 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA Linacre House, Jordan Hill, Oxford OX2 8DP, UK Copyright © 2007, Elsevier Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (⫹44) 1865 843830, fax: (⫹44) 1865 853333, E-mail: permissions@elsevier .com. You may also complete your request online via the Elsevier homepage (http://elsevier.com), by selecting “Support & Contact” then “Copyright and Permission” and then “Obtaining Permissions.” Recognizing the importance of preserving what has been written, Elsevier prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data (Application submitted.) British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. ISBN: 978-0-7506-8534-4 For information on all Newnes publications visit our Web site at www.books.elsevier.com 08 09 10 11 12 13 10 9 8 7 6 5 4 3 2 1 Typeset by Charon Tec Ltd (A Macmillan Company), Chennai, India www.charontec.com Printed in The United States of America

Table of Contents Foreword ..........................................................................................................xiii Preface ..............................................................................................................xiv Acknowledgments ..............................................................................................xv Terms and Abbreviations ...................................................................................xvi Conventions .................................................................................................... xviii References .........................................................................................................xix Chapter 1 – Introduction ...................................................................................... 1 What Is the ARM Cortex-M3 Processor? ............................................................................1 Background of ARM and ARM Architecture ......................................................................3 A Brief History ..............................................................................................................3 Architecture Versions .....................................................................................................4 Processor Naming ..........................................................................................................6 Instruction Set Development ................................................................................................8 The Thumb-2 Instruction Set Architecture (ISA) ................................................................9 Cortex-M3 Processor Applications ....................................................................................10 Organization of This Book .................................................................................................11 Further Readings ................................................................................................................11 Chapter 2 – Overview of the Cortex-M3 .............................................................. 13 Fundamentals ......................................................................................................................13 Registers .............................................................................................................................14 R0 to R12: General-Purpose Registers ........................................................................14 R13: Stack Pointers ......................................................................................................14 R14: The Link Register ................................................................................................15 R15: The Program Counter ..........................................................................................15 Special Registers ..........................................................................................................15 Operation Modes ................................................................................................................16 The Built-In Nested Vectored Interrupt Controller ............................................................17 Nested Interrupt Support ..............................................................................................18 Vectored Interrupt Support ...........................................................................................18 Dynamic Priority Changes Support .............................................................................18 Reduction of Interrupt Latency ....................................................................................18 Interrupt Masking ........................................................................................................18 v

Table of Contents The Memory Map ...............................................................................................................19 The Bus Interface ...............................................................................................................20 The Memory Protection Unit .............................................................................................20 The Instruction Set .............................................................................................................20 Interrupts and Exceptions ...................................................................................................22 Debugging Support .............................................................................................................24 Characteristics Summary ....................................................................................................25 High Performance ........................................................................................................25 Advanced Interrupt-Handling Features ........................................................................25 Low Power Consumption.............................................................................................26 System Features ...........................................................................................................26 Debug Supports ............................................................................................................26 Chapter 3 – Cortex-M3 Basics ............................................................................ 29 Registers .............................................................................................................................29 General-Purpose Registers R0–R7 ..............................................................................29 General-Purpose Registers R8–R12 ............................................................................29 Stack Pointer R13 ........................................................................................................30 Link Register R14 ........................................................................................................32 Program Counter R15 ..................................................................................................33 Special Registers ................................................................................................................33 Program Status Registers (PSRs) .................................................................................33 PRIMASK, FAULTMASK, and BASEPRI Registers .................................................35 The Control Register ....................................................................................................36 Operation Mode ..................................................................................................................37 Exceptions and Interrupts ...................................................................................................39 Vector Tables ......................................................................................................................40 Stack Memory Operations ..................................................................................................41 Basic Operations of the Stack ......................................................................................41 Cortex-M3 Stack Implementation................................................................................42 The Two-Stack Model in the Cortex-M3 .....................................................................43 Reset Sequence ...................................................................................................................44 Chapter 4 – Instruction Sets ............................................................................... 47 Assembly Basics .................................................................................................................47 Assembler Language: Basic Syntax ............................................................................47 Assembler Language: Use of Sufﬁ xes .........................................................................48 Assembler Language: Uniﬁ ed Assembler Language ...................................................49 Instruction List ...................................................................................................................50 Unsupported Instructions .............................................................................................55 Instruction Descriptions .....................................................................................................57 Assembler Language: Moving Data ............................................................................57 LDR and ADR Pseudo Instructions .............................................................................60 vi

Table of Contents Assembler Language: Processing Data ........................................................................61 Assembler Language: Call and Unconditional Branch ................................................66 Assembler Language: Decisions and Conditional Branches .......................................67 Assembler Language: Combined Compare and Conditional Branch ..........................70 Assembler Language: Conditional Branches Using IT Instructions ...........................71 Assembler Language: Instruction Barrier and Memory Barrier Instructions ..............72 Assembly Language: Saturation Operations ................................................................73 Several Useful Instructions in the Cortex-M3 ....................................................................75 MSR and MRS .............................................................................................................75 IF-THEN ......................................................................................................................76 CBZ and CBNZ ...........................................................................................................77 SDIV and UDIV ..........................................................................................................78 REV, REVH, and REVSH ...........................................................................................78 RBIT ............................................................................................................................78 SXTB, SXTH, UXTB, and UXTH ..............................................................................79 BFC and BFI ................................................................................................................79 UBFX and SBFX .........................................................................................................79 LDRD and STRD .........................................................................................................80 TBB and TBH ..............................................................................................................80 Chapter 5 – Memory Systems ............................................................................. 83 Memory System Features Overview ..................................................................................83 Memory Maps ....................................................................................................................83 Memory Access Attributes .................................................................................................86 Default Memory Access Permissions .................................................................................88 Bit-Band Operations ...........................................................................................................88 Advantages of Bit-Band Operations ............................................................................92 Bit-Band Operation of Different Data Sizes ................................................................95 Bit-Band Operations in C Programs ............................................................................95 Unaligned Transfers ...........................................................................................................96 Exclusive Accesses .............................................................................................................98 Endian Mode ....................................................................................................................100 Chapter 6 – Cortex-M3 Implementation Overview .............................................. 103 The Pipeline ......................................................................................................................103 A Detailed Block Diagram ...............................................................................................105 Bus Interfaces on the Cortex-M3 .....................................................................................108 The I-Code Bus ..........................................................................................................108 The D-Code Bus ........................................................................................................108 The System Bus .........................................................................................................109 The External Private Peripheral Bus ..........................................................................109 The Debug Access Port Bus ......................................................................................109 Other Interfaces on the Cortex-M3 ...................................................................................109 vii

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