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SPFD5408_ID5408.pdf

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    D A T A S H E E T SSPPFFDD55440088AA 772200--cchhaannnneell 66--bbiitt SSoouurrccee DDrriivveerr wwiitthh SSyysstteemm--oonn--cchhiipp ffoorr CCoolloorr AAmmoorrpphhoouuss TTFFTT--LLCCDDss PPrreelliimmiinnaarryy DEC. 20, 2006 Version 0.1 ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE.
    SPFD5408A Table of Contents PAGE 1. GENERAL DESCRIPTION...............................................................................................................................................................................5 2. FEATURE..........................................................................................................................................................................................................5 3. ORDERING INFORMATION.............................................................................................................................................................................5 4. BLOCK DIAGRAM............................................................................................................................................................................................6 4.1. BLOCK FUNCTION........................................................................................................................................................................................6 4.2. SYSTEM INTERFACE ....................................................................................................................................................................................7 4.2.1. The SPFD5408A supports three high-speed system interfaces:...............................................................................................7 4.2.2. External Display Interface...........................................................................................................................................................7 4.2.3. Address Counter (AC).................................................................................................................................................................7 4.2.4. Graphics RAM (GRAM)...............................................................................................................................................................7 4.2.5. Grayscale Voltage Generating Circuit........................................................................................................................................7 4.2.6. Timing Controller.........................................................................................................................................................................7 4.2.7. Oscillator (OSC)..........................................................................................................................................................................7 4.2.8. Source Driver Circuit...................................................................................................................................................................7 4.2.9. Gate Driver Circuit.......................................................................................................................................................................7 4.2.10. LCD Driving Power Supply Circuit..............................................................................................................................................7 5. SIGNAL DESCRIPTIONS.................................................................................................................................................................................8 6. INSTRUCTIONS..............................................................................................................................................................................................12 6.1. OUTLINE....................................................................................................................................................................................................12 6.2. INSTRUCTION ............................................................................................................................................................................................13 Index Register (IR)....................................................................................................................................................................14 6.2.1. 6.2.2. ID Read Register (SR)..............................................................................................................................................................14 6.2.3. Driver Output Control Register (R01h).....................................................................................................................................14 6.2.4. LCD Driving Waveform Control (R02h)....................................................................................................................................15 6.2.5. Entry Mode (R03h)....................................................................................................................................................................15 6.2.6. Scalling Control register (R04h)................................................................................................................................................16 6.2.7. Display Control (R07h)..............................................................................................................................................................16 6.2.8. Display Control 2 (R08h)...........................................................................................................................................................17 6.2.9. Display Control 3 (R09h)...........................................................................................................................................................18 6.2.10. Frame Cycle Control (R0Ah).....................................................................................................................................................19 6.2.11. External Display Interface Control 1 (R0Ch)............................................................................................................................20 6.2.12. Frame Maker Position (R0Dh)..................................................................................................................................................21 6.2.13. External Display Interface Control 2 (R0Fh).............................................................................................................................21 6.2.14. Power Control 1 (R10h)............................................................................................................................................................22 6.2.15. Power Control 2 (R11h).............................................................................................................................................................23 6.2.16. Power Control 3 (R12h)............................................................................................................................................................24 6.2.17. Power Control 4 (R13h)............................................................................................................................................................24 6.2.18. Power Control 5 (R17h)............................................................................................................................................................25 6.2.19. GRAM Address Set (Horizontal Address) (R20h)....................................................................................................................26 6.2.20. GRAM Address Set (Vertical Address) (R21h).........................................................................................................................26 6.2.21. Write Data to GRAM (R22h).....................................................................................................................................................27 6.2.22. Read Data Read from GRAM (R22h).......................................................................................................................................30 6.2.23. NVM read data 1 (R28h)...........................................................................................................................................................30 DEC. 20, 2006 Preliminary Version: 0.1 2 © ORISE Technology Co., Ltd. Proprietary & Confidential
    SPFD5408A 6.2.24. NVM read data 2 (R29h)...........................................................................................................................................................30 6.2.25. NVM read data 3 (R2Ah)...........................................................................................................................................................30 6.2.26. γ Control (R30h to R3Fh)..........................................................................................................................................................31 6.2.27. Window Horzontal RAM Address Start (R50h).........................................................................................................................31 6.2.28. Window Horzontal RAM Address End (R51h)..........................................................................................................................31 6.2.29. Window Vertical RAM Address Start (R52h)............................................................................................................................32 6.2.30. Window Vertical RAM Address End (R53h).............................................................................................................................32 6.2.31. Driver Output Control (R60h)....................................................................................................................................................32 6.2.32. Driver Output Control (R61h)....................................................................................................................................................33 6.2.33. Vertical Scroll Control (R6Ah)...................................................................................................................................................34 6.2.34. Display Position – Partial Display 1 (R80h)..............................................................................................................................34 6.2.35. RAM Address Start – Partial Display 1 (R81h).........................................................................................................................34 6.2.36. RAM address End – Partail Display 1 (R82h)..........................................................................................................................34 6.2.37. Display Position – Partial Display 2 (R83h)..............................................................................................................................35 6.2.38. RAM Address Start – Partial Display 2 (R84h).........................................................................................................................35 6.2.39. RAM Address End – Partial Display 2 (R85h)..........................................................................................................................35 6.2.40. Frame Cycle Control (R90h).....................................................................................................................................................35 6.2.41. Panel Interface Control 2 (R92h)..............................................................................................................................................36 6.2.42. Panel Interface control 3 (R93h)...............................................................................................................................................36 6.2.43. Frame Cycle Control (R95h).....................................................................................................................................................37 6.2.44. Panel Interface Control 5 (R97h)..............................................................................................................................................38 6.2.45. Panel Interface Control (R98h).................................................................................................................................................38 6.2.46. Calibration Control (RA4h)........................................................................................................................................................39 7. GRAM..............................................................................................................................................................................................................40 8. INTERFACES..................................................................................................................................................................................................42 8.1. SYSTEM INTERFACE ..................................................................................................................................................................................42 8.1.1. 80-system 18-bit interface.........................................................................................................................................................43 8.1.2. 80-system 16-bit interface.........................................................................................................................................................43 8.1.3. 80-system 9-bit interface...........................................................................................................................................................43 8.1.4. 80-system 8-bit interface...........................................................................................................................................................43 8.1.5. Serial Peripheral interface (SPI)...............................................................................................................................................44 8.2. VSYNC INTERFACE ..................................................................................................................................................................................45 8.3. EXTERNAL DISPLAY INTERFACE .................................................................................................................................................................46 8.3.1. 6-bit RGB interface....................................................................................................................................................................47 8.3.2. 16-bit RGB interface..................................................................................................................................................................48 8.3.3. 18-bit RGB interface..................................................................................................................................................................48 9. NVM ACCESS CONTROL:..................................................................................................................................................................................49 10. DISPLAY FEATURE FUNCTION:...........................................................................................................................................................................50 10.1. FMARK FUNCTION:...................................................................................................................................................................................50 10.2. SCAN MODE FUNCTION:.............................................................................................................................................................................51 10.3. SCALLING FUNCTION:................................................................................................................................................................................52 10.4. PARTIAL DISPLAY FUNCTION:.....................................................................................................................................................................54 10.5. GAMMA CORRECTION FUNCTION:...............................................................................................................................................................56 11. POWER MANAGEMENT SYSTEM:........................................................................................................................................................................57 12. APPLICATION CIRCUITS:....................................................................................................................................................................................60 © ORISE Technology Co., Ltd. Proprietary & Confidential 3 DEC. 20, 2006 Preliminary Version: 0.1
    SPFD5408A 13. INITIAL CODE:....................................................................................................................................................................................................61 14. ELECTRICAL CHARACTERISTICS:.......................................................................................................................................................................62 14.1. ABSOLUTE MAXIMUM RATINGS:.................................................................................................................................................................62 14.2. DC CHARACTERISTICS..............................................................................................................................................................................62 14.3. AC CHARACTERISTICS ..............................................................................................................................................................................63 14.3.1. Clock Characteristics.................................................................................................................................................................63 14.3.2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface).................................................................................63 14.3.3. Clock-synchronized Serial Interface Timing Characteristics...................................................................................................64 15. CHIP INFORMATION......................................................................................................................................................................................66 15.1. PAD ASSIGNMENT.....................................................................................................................................................................................66 15.2. PAD DIMENSION .......................................................................................................................................................................................66 15.3. BUMP DIMENSION......................................................................................................................................................................................66 15.3.1. Output Pads...............................................................................................................................................................................66 15.3.2. Input Pads..................................................................................................................................................................................66 15.4. PAD LOCATIONS .......................................................................................................................................................................................67 15.5. ALIGNMENT MARK .....................................................................................................................................................................................75 16. DISCLAIMER...................................................................................................................................................................................................76 17. REVISION HISTORY.......................................................................................................................................................................................77 © ORISE Technology Co., Ltd. Proprietary & Confidential 4 DEC. 20, 2006 Preliminary Version: 0.1
    SPFD5408A - High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports - Serial Peripheral Interface (SPI) n Interfaces for moving picture display 6-, 16-, and 18-bit RGB interfaces - n Diverse RAM accessing for functional display - Window address function to display at any area on the screen via a moving picture display interface - Window address function to limit the data rewriting area n System interfaces 720-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC) FOR COLOR AMORPHOUS TFT LCD 1. GENERAL DESCRIPTION The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The 720-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The SPFD5408A is able to operate with low IO interface power supply up to 1.6V and incorporate with several charge pumps to generate various voltage levels that form an on-chip power management system for gate driver and source driver. The built-in timing controller in SPFD5408A can support several interfaces for the diverse request of medium or small size portable display. SPFD5408A provides system interfaces, which include 8-/9-/16-/18-bit parallel interfaces and serial interface (SPI), to configure system. Not only can the system interfaces be used to configure system, they can also access RAM at high speed for still picture display. In addition, the SPFD5408A incorporates 6, 16, and 18-bit RGB interfaces for picture movement display. The SPFD5408A also supports a function to display eight colors and a standby mode for power control consideration. 2. FEATURE n One-chip solution for amorphous TFT-LCD. n Supports resolution up to 240xRGBx320, incorporating a 720-channel source driver and a 320-channel gate driver n Outputs 64 γ-corrected values using an internal true 6-bit VGH = 10.0V ~20.0V VGL = -4.5V ~ -13.5V VGH – VGL < 28.0V n Resize function( x 1/2, x 1/4) n On-chip power management system n Built-in Charge Pump circuits and reduce data transfer n Power supply - Moving and still picture can display at the same time - Vertical scrolling function - Partial screen display - Logic power supply voltage (Vcc): 2.5 ~ 3.3 V - I/O interface supply voltage (IOVcc): 1.65 ~ 3.3 V - Analog power supply voltage (Vci): 2.5 ~ 3.3 V - Power saving mode (standby / 8-color mode, etc) - Low power consumption structure for source driver. - Source driver voltage level : DDVDH-GND=4.5V ~ 6V. - Gate driver voltage level (VGH, VGL) - Built-in internal oscillator and hardware reset n Built–in One-Time-Programming (OTP) function for VCOM resolution D/A converter to achieve 262K colors n Built-in 172800 bytes internal RAM n Line Inversion AC drive / frame inversion AC drive 3. ORDERING INFORMATION Product Number SPFD5408A-C © ORISE Technology Co., Ltd. Proprietary & Confidential 5 amplitude and VcomH voltage adjustment. User identification code,4 bits, VCOM level adjustment, 5 bits x 2 sets Package Type Chip Form with Gold Bump DEC. 20, 2006 Preliminary Version: 0.1
    SPFD5408A OTP Memory Graphics RAM 172800 bytes 18 S1 S2 S719 S720 Source Driver (720 channels) True 6-bit D/A Converter 6 6 Level Shifter (720 x 6bits) 6 6 6 6 6 6 Data Latch (240 x 3 x 6bits) Shift Register (240 bits) VCIOUT Regulator VREG1OUT VCI1 C11P/N C12P/N C21P/N CLK C22P/N Gate Power Charge Pump VLOUT1 /DDVDH VLOUT2 /VGH VLOUT3 /VGL VLOUT4 /VCL Gamma Voltage Generator 64 VCOM VCOMH VCOM VCOML Gate Driver G[320:1] 4. BLOCK DIAGRAM 4.1. Block Function WR*/SCL SDI SDO IM[3:1],IM0/ID CS* RS DB[17:0] 18 ENABLE DOTCLK VSYNC HSYNC System Interface RGB Interface Timing Signal Generator Internal Clock Generator © ORISE Technology Co., Ltd. Proprietary & Confidential 6 DEC. 20, 2006 Preliminary Version: 0.1
    4.2. System Interface 4.2.1. The SPFD5408A supports three high-speed system interfaces: 1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 2. Serial Peripheral Interface (SPI). The SPFD5408A has a 16-bit index register (IR) and two 18-bit data registers, a write-data register (WDR) and a read-data register (RDR). The IR register is used to store index information from control registers. The WDR register is used to temporarily store data to be written for register control and internal GRAM. The RDR register is used to temporarily store data read from the GRAM. When graphic data is written to the internal GRAM from MCU/graphic engine, the data is first written to the WDR and then automatically written to the internal GRAM in internal operation. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore, invalid data is first read out to the data bus when the SPFD5408A executes the 1st read operation. Thus, valid data can be read out after the SPFD5408A executes the 2nd read operation. 4.2.2. External Display Interface The SPFD5408A supports external RGB interface for picture movement display. The SPFD5408A allows switching between one of the external display interfaces and the system interface via pin configuration so that the optimum interface is selected for still / moving picture displayed on the screen. When the RGB interface is chosen, display operations are synchronized with external supplied signals, VSYNC, HSYNC, and DOTCLK. Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling. 4.2.3. Address Counter (AC) SPFD5408A features an Address Counter (AC) giving an address to the internal GRAM. The address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. SPFD5408A 4.2.4. Graphics RAM (GRAM) SPFD5408A features a 172800-byte (240 x 320 x 18 / 8) Graphic RAM (GRAM). 4.2.5. Grayscale Voltage Generating Circuit γ-correction SPFD5408A has true 6-bit resolution D/A converter, which generates 64 Gamma-corrected values and cooperates with OP-AMP structure to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the register. 4.2.6. Timing Controller SPFD5408A has a timing controller, which can generate a timing signal for internal circuit operation such as gate output timing, RAM accessing timing, etc. 4.2.7. Oscillator (OSC) The SPFD5408A also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is halted to reduce power consumption. 4.2.8. Source Driver Circuit SPFD5408A consists of a 720-output source driver circuit (S1 ~ S720). Data in the GRAM are latched when the 720 input. The latched data controls the source driver and generates a drive waveform. 4.2.9. Gate Driver Circuit th bit data is SPFD5408A consists of a 320-output gate driver circuit (G1~G320). The gate driver circuit outputs gate driver signals at either VGH or VGL level. 4.2.10. LCD Driving Power Supply Circuit The LCD driving power supply circuit generates the voltage levels DDVDH, VLOUT1, VLOUT2 and VCOM for driving an LCD. All this voltages can be adjusted by register setting. © ORISE Technology Co., Ltd. Proprietary & Confidential 7 DEC. 20, 2006 Preliminary Version: 0.1
    SPFD5408A 5. SIGNAL DESCRIPTIONS Pin No. Signal System Configuration Input Signal IM3~1, IM0/ID 4 I GND/ IOVcc I/O Connected with Function Select a mode to interface to an MPU. In serial interface operation, the IM0 pin is used to set the ID bit of device code. IM3 Interface Mode DB Pin Colors IM2 IM1 IM0/ I D 0 1 0 0 0 0 0 0 0 0 1 Setting disabled Setting disabled - - 0 80-system 16-bit interface DB17-10, DB8-1 - - 262,144 see Note 1 262,144 see Note 2 65,536 - - - - DB17-10 - - - - - DB17-0 262,144 DB17-9 262,144 80-system 8-bit interface Clock synchronous serial interface Setting disabled Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 *(ID) 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Setting disabled Setting disabled Setting disabled Setting disabled - - - - - - - - /RESET 1 I MPU or external RC circuit Interface input Signals /CS 1 I MPU RS 1 I MPU (/WR) / (SCL) 1 I MPU Notes: 1. 65,536 colors in one transfer mode 2. 65,536 colors in two transfers mode RESET pin. This is an active low signal. Chip select signal. Low: the SPFD5408A is accessible High: the SPFD5408A is not accessible Must connect to the GND or IOVCC level when not used. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. Register select signal. Low: Index register or internal status is selected. High: Control register is selected. Must connect to the GND or IOVCC level when not used. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. (A) In 80-system interface mode, a write strobe signal can be input via this pin and initializes a write operation when the signal is low. (B) In SPI mode, served as a synchronizing clock signal. This pin has weak pull high/low resistors and can be modified to high / low by © ORISE Technology Co., Ltd. Proprietary & Confidential 8 DEC. 20, 2006 Preliminary Version: 0.1
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